3 Patents
- US121492552024Generating Divided Signals from Phase-locked Loop (PLL) Output When Reference Clock Is Unavailable
Shaoxing Yuanfang Semiconductor Co., Ltd.
0 cites - US119679652024Generating Divided Signals from Phase-locked Loop (PLL) Output When Reference Clock Is Unavailable
Shaoxing Yuanfang Semiconductor Co., Ltd.
0 cites - US115884892023Obtaining Lock in a Phase-locked Loop (PLL) Upon Being Out of Phase-lock
Shaoxing Yuanfang Semiconductor Co., Ltd.
0 cites