Nishith Desai

3 Patents

• US124230582025

  Systolic Array with Input Reduction to Multiple Reduced Inputs

  Amazon Technologies, Inc.

  0 cites
• US123332742025

  Data-type-aware Clock-gating

  Amazon Technologies, Inc.

  0 cites
• US118806822024

  Systolic Array with Efficient Input Reduction and Extended Array Performance

  Amazon Technologies, Inc.

  0 cites