Patents/Inventors

Nicola Del Gatto

Cassina de′ PecchiIT44 patents

27 Patents

US126137762026
Parity Cache for Raid Reliability, Accessibility, and Serviceability of a Memory Device
Micron Technology, Inc.
0 cites
US126082732026
RAS Triggers L2P Table Movement in CXL Devices with Compression
Micron Technology, Inc.
0 cites
US126021832026
Controller and Methods for Managing Timing Charcteristics Using Collected Metrics and a Telemetry Ratio
Micron Technology, Inc.
0 cites
US126023202026
Dynamic Page Mapping Using Header to Identify Compressed Data
Micron Technology, Inc.
0 cites
US125790312026
Read Data Path for a Memory System
Micron Technology, Inc.
0 cites
US125610792026
Dual-level Refresh Management
Micron Technology, Inc.
0 cites
US125612002026
Read Data Path
Micron Technology, Inc.
0 cites
US124232302025
Controller Cache Architeture
Micron Technology, Inc.
0 cites
US122993312025
Managed Memory Systems with Multiple Priority Queues
Micron Technology, Inc.
0 cites
US122824332025
Cache Bypass
Micron Technology, Inc.
0 cites
US122107712025
Arbitration Policy to Prioritize Read Command Dequeuing by Delaying Write Command Dequeuing
Micron Technology, Inc.
0 cites
US121647742024
Performance Throttling Module
Micron Technology, Inc.
0 cites
US121647732024
Controller Architecture for Reliability, Availability, Serviceability Access
Micron Technology, Inc.
0 cites
US121247292024
Controller to Alter Systems Based on Metrics and Telemetry
Micron Technology, Inc.
0 cites
US121059712024
Dual-level Refresh Management
Micron Technology, Inc.
0 cites
US120935662024
Memory Controller for Managing Raid Information
Micron Technology, Inc.
0 cites
US120864592024
Optimized Control of the Commands Running in a Cache
Micron Technology, Inc.
0 cites
US120391722024
Managing Performance Throttling in a Digital Controller
Micron Technology, Inc.
0 cites
US119890882024
Read Data Path
Micron Technology, Inc.
0 cites
US119777692024
Control of Back Pressure Based on a Total Number of Buffered Read and Write Entries
Micron Technology, Inc.
0 cites
US119540352024
Cache Architectures with Address Delay Registers for Memory Devices
Micron Technology, Inc.
0 cites
US119342702024
Write Command Execution for Data Protection and Recovery Schemes
Micron Technology, Inc.
0 cites
US119148932024
Managed Memory Systems with Multiple Priority Queues
Micron Technology, Inc.
0 cites
US118867492024
Interrupt Mode or Polling Mode for Memory Devices
Micron Technology, Inc.
0 cites
US117638872023
Cleaning Memory Blocks Using Multiple Types of Write Operations
Micron Technology, Inc.
0 cites
US117202842023
Low Latency Storage Based on Data Size
Micron Technology, Inc.
0 cites
US115617332023
Interrupt Mode or Polling Mode for Memory Devices
Micron Technology, Inc.
0 cites