Natarajan Viswanathan

5 Patents

• US126140142026

  Grouping Cells in Cell Library Based on Iterative Clustering

  Cadence Design Systems, Inc.

  0 cites
• US123397012025

  Insertion Delay and Area Tradeoff for Buffering Solution Selection in Clock Tree Synthesis

  Cadence Design Systems, Inc.

  0 cites
• US123211932025

  Hierarchically-aware Buffering for Clock Structures

  Cadence Design Systems, Inc.

  0 cites
• US116454412023

  Machine-learning Based Clustering for Clock Tree Synthesis

  Cadence Design Systems, Inc.

  0 cites
• US116255252023

  Grouping Cells in Cell Library Based on Clustering

  Cadence Design Systems, Inc.

  0 cites