Narayanan Ramanan

6 Patents

• US123944922025

  Memory Cell Sensing Circuit with Adjusted Bias from Pre-boost Operation

  Intel NDTM US LLC

  0 cites
• US123224552025

  Program Verify Process Having Placement Aware Pre-program Verify (PPV) Bucket Size Modulation

  Intel NDTM US LLC

  0 cites
• US122664062025

  NAND Sensing Circuit and Technique for Read-disturb Mitigation

  Intel NDTM US LLC

  0 cites
• US122370232025

  Dynamic Detection and Dynamic Adjustment of Sub-threshold Swing in a Memory Cell Sensing Circuit

  Intel NDTM US LLC

  0 cites
• US120873652024

  Modulation of Source Voltage in Nand-flash Array Read

  Intel NDTM US LLC

  0 cites
• US120514692024

  Method and Apparatus to Mitigate Hot Electron Read Disturbs in 3D Nand Devices

  Intel NDTM US LLC

  0 cites