81 Patents
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- US126082752026Multi-layer Code Rate Architecture for Copyback Between Partitions with Different Code Rates
Micron Technology, Inc.
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MICRON TECHNOLOGY, Inc.
0 cites - US124877582025Error Decoding with Soft Redundant Array of Independent NAND (RAIN)
MICRON TECHNOLOGY, Inc.
0 cites - US124126322025Managing Compensation for Charge Coupling and Lateral Migration in Memory Devices
Micron Technology, Inc.
0 cites - US123933632025Voltage Bin Calibration Based on a Voltage Distribution Reference Voltage
Micron Technology, Inc.
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Micron Technology, Inc.
0 cites - US123482442025Detecting a Stall Condition in Bit Flipping Decoding Using Syndrome Weight Slope
MICRON TECHNOLOGY, Inc.
0 cites - US123327432025Efficient Memory Use to Support Soft Information in Bit Flipping Decoders
MICRON TECHNOLOGY, Inc.
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- US123281292025Bypassing Iterations in a Bit Flipping Decoder Using a Least Reliable Bit Energy Function
MICRON TECHNOLOGY, Inc.
0 cites - US123267822025Adjustment of Code Rate as Function of Memory Endurance State Metric
Micron Technology, Inc.
0 cites - US123216132025Bit Flipping Decoder with Optimized Maximum Iterations for Varied Bit Flipping Thresholds
MICRON TECHNOLOGY, Inc.
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- US123012542025Early Stopping of Bit-flip Low Density Parity Check Decoding Based on Syndrome Weight
Micron Technology, Inc.
0 cites - US122664202025Temperature-compensated Time Estimate for a Block to Reach a Uniform Charge Loss State
Micron Technology, Inc.
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- US122231902025Measurement of Representative Charge Loss in a Block to Determine Charge Loss State
Micron Technology, Inc.
0 cites - US121977422025Managing Error Compensation Using Charge Coupling and Lateral Migration Sensitivity
Micron Technology, Inc.
0 cites - US121423332024Error Correction in a Memory Device Having an Error Correction Code of a Predetermined Code Rate
Micron Technology, Inc.
0 cites - US121190622024Managing Compensation for Cell-to-cell Coupling and Lateral Migration in Memory Devices Based on a Sensitivity Metric
Micron Technology, Inc.
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- US120873742024Managing Compensation for Cell-to-cell Coupling and Lateral Migration in Memory Devices Using Segmentation
Micron Technology, Inc.
0 cites - US120860282024Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate
Micron Technology, Inc.
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- US120463072024Managing Program Verify Voltage Offsets for Charge Coupling and Lateral Migration Compensation in Memory Devices
Micron Technology, Inc.
0 cites - US120462982024Managing Compensation for Charge Coupling and Lateral Migration in Memory Devices
Micron Technology, Inc.
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- US120140712024Separation of Parity Columns in Bit-flip Decoding of Low-density Parity-check Codes with Pipelining and Column Parallelism
Micron Technology, Inc.
0 cites - US119968602024Scaled Bit Flip Thresholds Across Columns for Irregular Low Density Parity Check Decoding
Micron Technology, Inc.
0 cites - US119949472024Multi-layer Code Rate Architecture for Special Event Protection with Reduced Performance Penalty
Micron Technology, Inc.
0 cites - US119830672024Adjustment of Code Rate as Function of Memory Endurance State Metric
MICRON TECHNOLOGY, Inc.
0 cites - US119666162024Voltage Bin Calibration Based on a Voltage Distribution Reference Voltage
Micron Technology, Inc.
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- US119157762024Error Avoidance Based on Voltage Distribution Parameters of Block Families
Micron Technology, Inc.
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- US118867182024Descrambling of Scrambled Linear Codewords Using Non-linear Scramblers
Micron Technology, Inc.
0 cites - US118863362024Managing Workload of Programming Sets of Pages to Memory Device
Micron Technology, Inc.
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- US118696052024Adjusting Pass-through Voltage Based on Threshold Voltage Shift
Micron Technology, Inc.
0 cites - US118686392024Providing Recovered Data to a New Memory Cell at a Memory Sub-system Based on an Unsuccessful Error Correction Operation
MICRON TECHNOLOGY, Inc.
0 cites - US118546492023Temperature-compensated Time Estimate for a Block to Reach a Uniform Charge Loss State
Micron Technology, Inc.
0 cites - US118473172023Managing Bin Placement for Block Families of a Memory Device Based on Trigger Metric Valves
Micron Technology, Inc.
0 cites - 0 cites
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- US118292452023Multi-layer Code Rate Architecture for Copyback Between Partitions with Different Code Rates
Micron Technology, Inc.
0 cites - US118237482023Voltage Bin Calibration Based on a Temporary Voltage Shift Offset
Micron Technology, Inc.
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- US117972052023Measurement of Representative Charge Loss in a Block to Determine Charge Loss State
Micron Technology, Inc.
0 cites - 0 cites
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- US117352542023Error Avoidance Based on Voltage Distribution Parameters of Blocks
Micron Technology, Inc.
0 cites - US117279942023Performing Threshold Voltage Offset Bin Selection by Package for Memory Devices
Micron Technology, Inc.
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- US117147102023Providing Data of a Memory System Based on an Adjustable Error Rate
Micron Technology, Inc.
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- US117105272023Mitigating a Voltage Condition of a Memory Cell in a Memory Sub-system
Micron Technology, Inc.
0 cites - US117110952023Bit Flipping Low-density Parity-check Decoders with Low Error Floor
Micron Technology, Inc.
0 cites - 0 cites
- US117051922023Managing Read Level Voltage Offsets for Low Threshold Voltage Offset Bin Placements
Micron Technology, Inc.
0 cites - 0 cites
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- US116766642023Voltage Bin Selection for Blocks of a Memory Device After Power Up of the Memory Device
Micron Technology, Inc.
0 cites - 0 cites
- US116755292023Threshold Voltage Determination for Calibrating Voltage Bins of a Memory Device
Micron Technology, Inc.
0 cites - 0 cites
- US116200742023Voltage Bin Calibration Based on a Voltage Distribution Reference Voltage
Micron Technology, Inc.
0 cites - US116098462023Managing Workload of Programming Sets of Pages to Memory Device
Micron Technology, Inc.
0 cites - 0 cites
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- US115564172023Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate
Micron Technology, Inc.
0 cites