3 Patents
- US125124112025Wafer-level ASIC 3D Integrated Substrate, Packaging Device and Preparation Method
SJ Semiconductor(jiangyin) Corporation
0 cites - US124827592025Wafer-level ASIC 3D Integrated Substrate, Packaging Device and Preparation Method
SJ Semiconductor(jiangyin) Corporation
0 cites - US118429762023Semiconductor Package Structure with Heat Sink and Method Preparing the Same
SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
0 cites