Patents/Inventors

Mike Macpherson

Portland, ORUS36 patents

34 Patents

US125612762026
Systems and Methods for Updating Memory Side Caches in a Multi-gpu Configuration
INTEL CORPORATION
0 cites
US125612772026
Memory Controller Management Techniques for Managing Data Transfer for Memory Access Operations
INTEL CORPORATION
0 cites
US125546742026
Multi-tile Memory Management
Intel Corporation
0 cites
US123996852025
Systolic Array Having Support for Output Sparsity
Intel Corporation
0 cites
US123739122025
Prefetch Status Notification for Memory Prefetching
INTEL CORPORATION
0 cites
US123466942025
Register File for Systolic Array
Intel Corporation
0 cites
US123213102025
Implicit Fence for Write Messages
Intel Corporation
0 cites
US122934312025
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US122545262025
On Chip Dense Memory for Temporal Buffering
Intel Corporation
0 cites
US122424142025
Data Initialization Techniques
INTEL CORPORATION
0 cites
US122298672025
Graphics Architecture Including a Neural Network Pipeline
Intel Corporation
0 cites
US122104772025
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites
US122044872025
Graphics Processor Data Access and Sharing
INTEL CORPORATION
0 cites
US121982222025
Architecture for Block Sparse Operations on a Systolic Array
Intel Corporation
0 cites
US121820622024
Multi-tile Memory Management
Intel Corporation
0 cites
US121535412024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US121410942024
Systolic Disaggregation Within a Matrix Accelerator Architecture
Intel Corporation
0 cites
US121179622024
Scalar Core Integration
INTEL CORPORATION
0 cites
US120994612024
Multi-tile Memory Management
INTEL CORPORATION
0 cites
US120932102024
Compression Techniques
INTEL CORPORATION
0 cites
US120791552024
Graphics Processor Operation Scheduling for Deterministic Latency
Intel Corporation
0 cites
US120669752024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US120019442024
Tool for Facilitating Efficiency in Machine Learning
INTEL CORPORATION
0 cites
US119950292024
Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-tile Inference Scaling and Providing Page Migration
Intel Corporation
0 cites
US119343422024
Assistance for Hardware Prefetch in Cache Access
INTEL CORPORATION
0 cites
US118996142024
Instruction Based Control of Memory Attributes
Intel Corporation
0 cites
US118929502024
Data Prefetching for Graphics Data Processing
INTEL CORPORATION
0 cites
US118617592024
Memory Prefetching in Multiple GPU Environment
INTEL CORPORATION
0 cites
US118424232023
Dot Product Operations on Sparse Matrix Elements
Intel Corporation
0 cites
US118099052023
Local Memory Sharing Between Kernels
Intel Corporation
0 cites
US117628042023
Scalar Core Integration
INTEL CORPORATION
0 cites
US116762392023
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US116763222023
Graphics Architecture Including a Neural Network Pipeline
Intel Corporation
0 cites
US116202562023
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites