Michael David Jager

2 Patents

• US126160432026

  Package Comprising Integrated Devices with Inner and Outer Solder Interconnects

  QUALCOMM INCORPORATED

  0 cites
• US116627652023

  System for Providing a Low Latency and Fast Switched Cascaded Dual Phased Lock Loop (PLL) Architecture for Die-to-die / System-on-chip (soc) Interfaces

  QUALCOMM Incorporated

  0 cites