Patents/Inventors

Mayukh Bhattacharya

Palo Alto, CAUS11 patents

10 Patents

US125305152026
Maximizing Detectable Defect Coverage of Analog Circuits in Integrated Circuit Design
Synopsys, Inc.
0 cites
US124818132025
Test Point Insertion in Analog Circuit Design Testing
Synopsys, Inc.
0 cites
US123323012025
Measuring Device Defect Sensitization in Transistor-level Circuits
Synopsys, Inc.
0 cites
US122716682025
Finding Equivalent Classes of Hard Defects in Stacked MOSFET Arrays
Synopsys, Inc.
0 cites
US117977372023
Finding Equivalent Classes of Hard Defects in Stacked MOSFET Arrays
Synopsys, Inc.
0 cites
US117630562023
Method and System for Custom Model Definition of Analog Defects in an Integrated Circuit
Synopsys, Inc.
0 cites
US117344822023
Visual Representation to Assess Quality of Input Stimulus in Transistor-level Circuits
Synopsys, Inc.
0 cites
US116696672023
Automatic Test Pattern Generation (ATPG) for Parametric Faults
Synopsys, Inc.
0 cites
US116204242023
Transistor—level Defect Coverage and Defect Simulation
Synopsys, Inc.
0 cites
US115799942023
Fast and Scalable Methodology for Analog Defect Detectability Analysis
Synopsys, Inc.
0 cites