17 Patents
- US125849612026Built-in Self Test Circuit for Segmented Static Random Access Memory (SRAM) Array Input/output
Stmicroelectronics International N.V.
0 cites - US124825182025Enhanced Accuracy of Bit Line Reading for an In-memory Compute Operation by Accounting for Variation in Read Current
Stmicroelectronics International N.V.
0 cites - US124695452025Bit Line Read Current Mirroring Circuit for an In-memory Compute Operation Where Simultaneous Access Is Made to Plural Rows of a Static Random Access Memory (SRAM)
Stmicroelectronics International N.V.
0 cites - US124378252025At-speed Transition Fault Testing for a Multi-port and Multi-clock Memory
Stmicroelectronics International N.V.
0 cites - US124067052025In-memory Computation Circuit Using Static Random Access Memory (SRAM) Array Segmentation
Stmicroelectronics International N.V.
0 cites - US123865062025Tagged Memory Operated at Lower VMIN in Error Tolerant System
Stmicroelectronics International N.V.
0 cites - US123619822025Memory Architecture Supporting Both Conventional Memory Access Mode and Digital In-memory Computation Processing Mode
Stmicroelectronics International N.V.
0 cites - US123533412025Tuning of Read/write Cycle Time Delay for a Memory Circuit Dependent on Operational Mode Selection
Stmicroelectronics International N.V.
0 cites - US123546442025Adaptive Word Line Underdrive Control for an In-memory Compute Operation Where Simultaneous Access Is Made to Plural Rows of a Static Random Access Memory (SRAM)
Stmicroelectronics International N.V.
0 cites - US122370072025Selective Bit Line Clamping Control for an In-memory Compute Operation Where Simultaneous Access Is Made to Plural Rows of a Static Random Access Memory (SRAM)
Stmicroelectronics International N.V.
0 cites - 0 cites
- US121760252024Adaptive Body Bias Management for an In-memory Compute Operation Where Simultaneous Access Is Made to Plural Rows of a Static Random Access Memory (SRAM)
Stmicroelectronics International N.V.
0 cites - US121701202024Built-in Self Test Circuit for Segmented Static Random Access Memory (SRAM) Array Input/output
Stmicroelectronics International N.V.
0 cites - US120873562024Serial Word Line Actuation with Linked Source Voltage Supply Modulation for an In-memory Compute Operation Where Simultaneous Access Is Made to Plural Rows of a Static Random Access Memory (SRAM)
Stmicroelectronics International N.V.
0 cites - US119841512024Adaptive Bit Line Overdrive Control for an In-memory Compute Operation Where Simultaneous Access Is Made to Plural Rows of a Static Random Access Memory (SRAM)
Stmicroelectronics International N.V.
0 cites - US119002402024Variable Clock Adaptation in Neural Network Processors
Stmicroelectronics International N.V.
0 cites - US118363462023Tagged Memory Operated at Lower Vmin in Error Tolerant System
Stmicroelectronics International N.V.
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