11 Patents
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- US124263162025Method of Fabricating Integrated Circuits with Fin Trim Plug Structures Having an Oxidation Catalyst Layer Surrounded by a Recessed Dielectric Material
Intel Corporation
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- US123693932025Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Approach
Intel Corporation
0 cites - US123493942025Dielectric Isolation Layer Between a Nanowire Transistor and a Substrate
Intel Corporation
0 cites - 0 cites
- US121319912024Self Aligned Gratings for Tight Pitch Interconnects and Methods of Fabrication
Intel Corporation
0 cites - US120028102024Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Approach
Intel Corporation
0 cites - 0 cites
- US119014582024Dielectric Isolation Layer Between a Nanowire Transistor and a Substrate
Intel Corporation
0 cites - 0 cites