Patents/Inventors

Lee D. Whetsel

Parker, TXUS56 patents

59 Patents

US125718402026
Array of Through-silicon via Contact Points on a Semiconductor Die
TEXAS INSTRUMENTS INCORPORATED
0 cites
US125409742026
Multiple Access Port Circuits
TEXAS INSTRUMENTS INCORPORATED
0 cites
US124679712025
Scan Testing Using Scan Frames with Embedded Commands
TEXAS INSTRUMENTS INCORPORATED
0 cites
US124611482025
3D Stacked Die Test Architecture
TEXAS INSTRUMENTS INCORPORATED
0 cites
US124166702025
Falling Clock Edge JTAG Bus Routers
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123793932025
Testing Interposer Method and Apparatus
TEXAS INSTRUMENTS INCORPORATED
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US123528142025
Interposer Circuit
TEXAS INSTRUMENTS INCORPORATED
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US123136672025
Integrated Circuit Die Test Architecture
TEXAS INSTRUMENTS INCORPORATED
0 cites
US122100602025
Device Access Port Selection
TEXAS INSTRUMENTS INCORPORATED
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US121889802025
Test Access Port with Address and Command Capability
TEXAS INSTRUMENTS INCORPORATED
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US121815212024
At-speed Test Access Port Operations
TEXAS INSTRUMENTS INCORPORATED
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US121639982024
TSV Testing
TEXAS INSTRUMENTS INCORPORATED
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US121640012024
3D Tap and Scan Port Architectures
TEXAS INSTRUMENTS INCORPORATED
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US121530902024
Commanded JTAG Test Access Port Operations
TEXAS INSTRUMENTS INCORPORATED
0 cites
US121548352024
Scan Testable Through Silicon Vias
TEXAS INSTRUMENTS INCORPORATED
0 cites
US121469092024
Selectable JTAG or Trace Access with Data Store and Output
TEXAS INSTRUMENTS INCORPORATED
0 cites
US121303282024
Interface to Full and Reduced Pin JTAG Devices
Texas Instruments Incorporated
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US121174902024
Scan Frame Based Test Access Mechanisms
Texas Instruments Incorporated
0 cites
US120926872024
Selectable JTAG or Trace Access with Data Store and Output
Texas Instruments Incorporated
0 cites
US120502472024
Addressable Test Access Port
Texas Instruments Incorporated
0 cites
US120256492024
Integrated Circuit Die Test Architecture
Texas Instruments Incorporated
0 cites
US120134342024
Programmable Test Compression Architecture Input/output Shift Register Coupled to SCI/SCO/PCO
Texas Instruments Incorporated
0 cites
US120074412024
3D Stacked Die Test Architecture
Texas Instruments Incorporated
0 cites
US119659302024
Test Compression in a JTAG Daisy-chain Environment
Texas Instruments Incorporated
0 cites
US119065822024
Shadow Access Port Method and Apparatus
Texas Instruments Incorporated
0 cites
US118799412024
Scan Testing Using Scan Frames with Embedded Commands
Texas Instruments Incorporated
0 cites
US118677562024
Reduced Signaling Interface Method and Apparatus
Texas Instruments Incorporated
0 cites
US118602242024
Interposer Instrumentation Method and Apparatus
Texas Instruments Incorporated
0 cites
US118546542023
Two Pin Serial Bus Communication Interface and Process
Texas Instruments Incorporated
0 cites
US118466732023
Device Testing Architecture, Method, and System
Texas Instruments Incorporated
0 cites
US118355732023
TSV Testing Method and Apparatus
Texas Instruments Incorporated
0 cites
US118355782023
Selectable JTAG or Trace Access with Data Store and Output
Texas Instruments Incorporated
0 cites
US118355812023
Interposer Circuit
Texas Instruments Incorporated
0 cites
US118088102023
At-speed Test Access Port Operations
Texas Instruments Incorporated
0 cites
US117820912023
Wafer Scale Testing Using a 2 Signal JTAG Interface
Texas Instruments Incorporated
0 cites
US117682382023
Integrated Circuit with Reduced Signaling Interface
Texas Instruments Incorporated
0 cites
US117620142023
3D TAP and Scan Port Architectures
Texas Instruments Incorporated
0 cites
US117473972023
Addressable Test Access Port Apparatus
Texas Instruments Incorporated
0 cites
US117402862023
Scan Testing Using Scan Frames with Embedded Commands
Texas Instruments Incorporated
0 cites
US117261352023
Integrated Circuit Die Test Architecture
Texas Instruments Incorporated
0 cites
US116930552023
Direct Scan Access JTAG
Texas Instruments Incorporated
0 cites
US116809812023
Test Access Port with Address and Command Capability
Texas Instruments Incorporated
0 cites
US116809852023
Falling Clock Edge JTAG Bus Routers
Texas Instruments Incorporated
0 cites
US116750072023
3D Stacked Die Test Architecture
Texas Instruments Incorporated
0 cites
US116562782023
Apparatus for Device Access Port Selection
Texas Instruments Incorporated
0 cites
US116444822023
Testing Interposer Method and Apparatus
Texas Instruments Incorporated
0 cites
US116445032023
TSV Testing Using Test Circuits and Grounding Means
Texas Instruments Incorporated
0 cites
US116399632023
Test Compression in a JTAG Daisy-chain Environment
Texas Instmments Incorporated
0 cites
US116354642023
Scan Frame Based Test Access Mechanisms
Texas Instruments Incorporated
0 cites
US116301512023
Interface to Full and Reduced Pin JTAG Devices
Texas Instruments Incorporated
0 cites
US116092692023
Device Testing Architecture of an Integrated Circuit
Texas Instruments Incorporated
0 cites
US116042222023
Commanded JTAG Test Access Port Operations
Texas Instmments Incorporated
0 cites
US115858512023
IEEE 1149.1 Interposer Apparatus
TEXAS INSTRUMENTS INCORPORATED
0 cites
US115858522023
At-speed Test Access Port Operations
TEXAS INSTRUMENTS INCORPORATED
0 cites
US115791932023
Shadow Access Port Integrated Circuit
TEXAS INSTRUMENTS INCORPORATED
0 cites
US115671312023
Programmable Test Compression Architecture Input/output Shift Register Coupled to SCI/SCO/PCO
TEXAS INSTRUMENTS INCORPORATED
0 cites
US115612582023
Wafer Scale Testing Using a 2 Signal JTAG Interface
TEXAS INSTRUMENTS INCORPORATED
0 cites
US115499822023
JTAG Bus Communication Method and Apparatus
Texas Instruments Incorporated
0 cites
US115499832023
3D Tap and Scan Port Architectures
TEXAS INSTRUMENTS INCORPORATED
0 cites