Patents/Inventors

Lars Liebmann

Mechanicville, NYUS41 patents

40 Patents

US125858572026
Method for Automated Standard Cell Design
Tokyo Electron Limited
0 cites
US125686512026
Semiconductor Structure Having Stacked Gates and Method of Manufacture Thereof
Tokyo Electron Limited
0 cites
US125573772026
Inverted Cross-couple for Top-tier FET for Multi-tier Gate-on-gate 3DI
Tokyo Electron Limited
0 cites
US125573922026
Highly Regular Logic Design for Efficient 3D Integration
Tokyo Electron Limited
0 cites
US124462912025
Inverted Top-tier FET for Multi-tier Gate-on-gate 3-dimension Integration (3di)
TOKYO ELECTRON LIMITED
0 cites
US124143672025
Tapered Device for Lateral Gate All Around Devices
Tokyo Electron Limited
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US123549912025
Replacement Buried Power Rail in Backside Power Delivery
Tokyo Electron Limited
0 cites
US123362742025
Self-aligned Method for Vertical Recess for 3D Device Integration
Tokyo Electron Limited
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US122373332025
Power Wall Integration for Multiple Stacked Devices
Tokyo Electron Limited
0 cites
US122242812025
Interdigitated Device Stack
TOKYO ELECTRON LIMITED
0 cites
US122180662025
Monolithic Formation of a Set of Interconnects Below Active Devices
Tokyo Electron Limited
0 cites
US122181352025
Wiring in Diffusion Breaks in an Integrated Circuit
Tokyo Electron Limited
0 cites
US121762932024
Inter-tier Power Delivery Network (PDN) for Dense Gate-on-gate 3D Logic Integration
TOKYO ELECTRON LIMITED
0 cites
US121319942024
Metallization Lines on Integrated Circuit Products
GLOBALFOUNDRIES U.S. Inc.
0 cites
US120876402024
High Density Logic Formation Using Multi-dimensional Laser Annealing
Tokyo Electron Limited
0 cites
US120516382024
Integrated High Efficiency Transistor Cooling
Tokyo Electron Limited
0 cites
US120402712024
Power Delivery Network for CFET with Buried Power Rails
Tokyo Electron Limited
0 cites
US120209902024
Method for Threshold Voltage Tuning Through Selective Deposition of High-k Metal Gate (HKMG) Film Stacks
Tokyo Electron Limited
0 cites
US120149842024
Method of Manufacturing a Semiconductor Apparatus Having Stacked Devices
Tokyo Electron Limited
0 cites
US120028622024
Inter-level Handshake for Dense 3D Logic Integration
Tokyo Electron Limited
0 cites
US119618022024
Power-tap Pass-through to Connect a Buried Power Rail to Front-side Power Distribution Network
Tokyo Electron Limited
0 cites
US119233642024
Double Cross-couple for Two-row Flip-flop Using CFET
Tokyo Electron Limited
0 cites
US119013602024
Architecture Design and Process for Manufacturing Monolithically Integrated 3D CMOS Logic and Memory
Tokyo Electron Limited
0 cites
US118308522023
Multi-tier Backside Power Delivery Network for Dense Gate-on-gate 3D Logic
TOKYO ELECTRON LIMITED
0 cites
US117912632023
Metallization Lines on Integrated Circuit Products
GLOBALFOUNDRIES U.S. Inc.
0 cites
US117912712023
Monolithic Formation of a Set of Interconnects Below Active Devices
Tokyo Electron Limited
0 cites
US117641132023
Method of 3D Logic Fabrication to Sequentially Decrease Processing Temperature and Maintain Material Thermal Thresholds
Tokyo Electron Limited
0 cites
US117642662023
Three-dimensional Semiconductor Device
Tokyo Electron Limited
0 cites
US117355252023
Power Delivery Network for CFET with Buried Power Rails
TOKYO ELECTRON LIMITED
0 cites
US117231872023
Three-dimensional Memory Cell Structure
Tokyo Electron Limited
0 cites
US117149452023
Method for Automated Standard Cell Design
Tokyo Electron Limited
0 cites
US116769682023
Coaxial Contacts for 3D Logic and Memory
Tokyo Electron Limited
0 cites
US116658782023
CFET SRAM Bit Cell with Two Stacked Device Decks
Tokyo Electron Limited
0 cites
US116463182023
Connections from Buried Interconnects to Device Terminals in Multiple Stacked Devices Structures
Tokyo Electron Limited
0 cites
US116316712023
3D Complementary Metal Oxide Semiconductor (CMOS) Device and Method of Forming the Same
Tokyo Electron Limited
0 cites
US116160202023
Power Distribution Network for 3D Logic and Memory
Tokyo Electron Limited
0 cites
US115812422023
Integrated High Efficiency Gate on Gate Cooling
Tokyo Electron Limited
0 cites
US115748452023
Apparatus and Method for Simultaneous Formation of Diffusion Break, Gate Cut, and Independent N and P Gates for 3D Transistor Devices
TOKYO ELECTRON LIMITED
0 cites
US115509852023
Method for Automated Standard Cell Design
Tokyo Electron Limited
0 cites
US115454972023
CFET SRAM Bit Cell with Three Stacked Device Decks
Tokyo Electron Limited
0 cites