Patents/Inventors

Lakshmi Kalpana Vakati

San Jose, CAUS9 patents

9 Patents

US124988862025
Buffer Allocation for Reducing Block Transit Penalty
MICRON TECHNOLOGY, Inc.
0 cites
US124814632025
Multiple-pass Programming of Memory Cells Using Temporary Parity Generation
MICRON TECHNOLOGY, Inc.
0 cites
US123401262025
Workload-based Scan Optimization
Micron Technology, Inc.
0 cites
US122044222025
Multiple Plane Programming with Quick Plane Programming Termination and Lagging Plane Boosting
Micron Technology, Inc.
0 cites
US120795172024
Buffer Allocation for Reducing Block Transit Penalty
MICRON TECHNOLOGY, Inc.
0 cites
US120514792024
Memory Block Programming Using Defectivity Information
MICRON TECHNOLOGY, Inc.
0 cites
US120017212024
Multiple-pass Programming of Memory Cells Using Temporary Parity Generation
MICRON TECHNOLOGY, Inc.
0 cites
US119777782024
Workload-based Scan Optimization
Micron Technology, Inc.
0 cites
US119070662024
Managing Storage of Multiple Plane Parity Data in a Memory Sub-system
Micron Technology, Inc.
0 cites