Patents/Inventors

Kuiwon Kang

San Diego, CAUS16 patents

17 Patents

US126108692026
Integrated Circuit (IC) Package Employing a Metal Block with Metal Interconnects Thermally Coupling a Die to an Interposer Substrate for Dissipating Thermal Energy of the Die, and Related Fabrication Methods
QUALCOMM INCORPORATED
0 cites
US125934082026
Package Substrate Having Embedded Electronic Component in a Core of the Package Substrate
QUALCOMM INCORPORATED
0 cites
US125819662026
Electronic Component Placed on Core of Substrate
QUALCOMM INCORPORATED
0 cites
US125001462025
Substrate(s) for an Integrated Circuit (IC) Package Employing a Metal Core for Improved Electrical Shielding and Structural Strength, and Related IC Packages and Fabrication Methods
QUALCOMM INCORPORATED
0 cites
US124245592025
Package with a Substrate Comprising Embedded Escape Interconnects and Surface Escape Interconnects
QUALCOMM INCORPORATED
0 cites
US123622692025
Integrated Circuit (IC) Packages Employing Supplemental Metal Layer Coupled to Embedded Metal Traces in a Die-side Embedded Trace Substrate (ETS) Layer, and Related Fabrication Methods
QUALCOMM INCORPORATED
0 cites
US123549352025
Integrated Circuit (IC) Package Substrate with Embedded Trace Substrate (ETS) Layer on a Substrate, and Related Fabrication Methods
QUALCOMM INCORPORATED
0 cites
US117913202023
Integrated Circuit (IC) Packages Employing a Package Substrate with a Double Side Embedded Trace Substrate (ETS), and Related Fabrication Methods
QUALCOMM INCORPORATED
0 cites
US117768882023
Package with a Substrate Comprising Protruding Pad Interconnects
QUALCOMM INCORPORATED
0 cites
US117640762023
Semi-embedded Trace Structure with Partially Buried Traces
QUALCOMM INCORPORATED
0 cites
US116769052023
Integrated Circuit (IC) Package with Stacked Die Wire Bond Connections, and Related Methods
QUALCOMM INCORPORATED
0 cites
US116370572023
Uniform via Pad Structure Having Covered Traces Between Partially Covered Pads
QUALCOMM INCORPORATED
0 cites
US116055952023
Packages with Local High-density Routing Region Embedded Within an Insulating Layer
QUALCOMM INCORPORATED
0 cites
US115520152023
Substrate Comprising a High-density Interconnect Portion Embedded in a Core Layer
QUALCOMM INCORPORATED
0 cites
US115520232023
Passive Component Embedded in an Embedded Trace Substrate (ETS)
QUALCOMM Incorporated
0 cites
US115454352023
Double Sided Embedded Trace Substrate
QUALCOMM INCORPORATED
0 cites
US115454392023
Package Comprising an Integrated Device Coupled to a Substrate Through a Cavity
QUALCOMM INCORPORATED
0 cites