19 Patents
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- US125686512026Semiconductor Structure Having Stacked Gates and Method of Manufacture Thereof
Tokyo Electron Limited
0 cites - US125640272026Top-down Self-alignment of Vias in a Semiconductor Device for Sub-22nm Pitch Metals
Tokyo Electron Limited
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- US123362742025Self-aligned Method for Vertical Recess for 3D Device Integration
Tokyo Electron Limited
0 cites - US120209902024Method for Threshold Voltage Tuning Through Selective Deposition of High-k Metal Gate (HKMG) Film Stacks
Tokyo Electron Limited
0 cites - US119013602024Architecture Design and Process for Manufacturing Monolithically Integrated 3D CMOS Logic and Memory
Tokyo Electron Limited
0 cites - US117696772023Substrate Processing Tool with Integrated Metrology and Method of Using
Tokyo Electron Limited
0 cites - US117053692023Fully Self-aligned via with Selective Bilayer Dielectric Regrowth
Tokyo Electron Limited
0 cites - US117007782023Method for Controlling the Forming Voltage in Resistive Random Access Memory Devices
Tokyo Electron Limited
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- US116580682023Method of Selective Deposition for Forming Fully Self-aligned Vias
Tokyo Electron Limited
0 cites - US116462272023Method of Forming a Semiconductor Device with Air Gaps for Low Capacitance Interconnects
Tokyo Electron Limited
0 cites - US116211902023Method for Filling Recessed Features in Semiconductor Devices with a Low-resistivity Metal
Tokyo Electron Limited
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- US116160532023Method to Vertically Route a Logic Cell Incorporating Stacked Transistors in a Three Dimensional Logic Device
Tokyo Electron Limited
0 cites - US115944512023Platform and Method of Operating for Integrated End-to-end Fully Self-aligned Interconnect Process
Tokyo Electron Limited
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