Joseph Michael Mccrate

2 Patents

• US120207432024

  Memory Device Architecture Using Multiple Physical Cells per Bit to Improve Read Margin and to Alleviate the Need for Managing Demarcation Read Voltages

  Micron Technology, Inc.

  0 cites
• US116054182023

  Memory Device Architecture Using Multiple Physical Cells per Bit to Improve Read Margin and to Alleviate the Need for Managing Demarcation Read Voltages

  Micron Technology, Inc.

  0 cites