Patents/Inventors

Jorge Parra

El Dorado Hills, CAUS17 patents

16 Patents

US124301282025
Sharing Register File Usage Between Fused Processing Resources
Intel Corporation
0 cites
US124057872025
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US123996852025
Systolic Array Having Support for Output Sparsity
Intel Corporation
0 cites
US123466942025
Register File for Systolic Array
Intel Corporation
0 cites
US121895712025
Dual Pipeline Parallel Systolic Array
Intel Corporation
0 cites
US121901582025
Using Sparsity Metadata to Reduce Systolic Array Power Consumption
Intel Corporation
0 cites
US121747832024
Systolic Array of Arbitrary Physical and Logical Depth
Intel Corporation
0 cites
US120932132024
Computing Efficient Cross Channel Operations in Parallel Computing Machines Using Systolic Arrays
INTEL CORPORATION
0 cites
US120390012024
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US120079352024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US120080672024
Sparse Matrix Multiplication Acceleration Mechanism
Intel Corporation
0 cites
US119778852024
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US119540632024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US117097932023
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US116694902023
Computing Efficient Cross Channel Operations in Parallel Computing Machines Using Systolic Arrays
INTEL CORPORATION
0 cites
US116361742023
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites