John Pillar

3 Patents

• US122671532025

  Frame Scheduling Based on an Estimated Direct Memory Access (DMA) Latency and Apparatus for Time Aware Frame Scheduling

  NXP B.V.

  0 cites
• US119241022024

  Minimizing Deviation from Average Latency of Table Lookups

  NXP B.V.

  0 cites
• US116377842023

  Method and System for Effective Use of Internal and External Memory for Packet Buffering Within a Network Device

  NXP USA, Inc.

  0 cites