Jitendra Kumar Yadav

6 Patents

• US124250322025

  Ring Voltage Controlled Oscillator-based Phase Locked Loop with Dual Charge Pump Architecture

  Cadence Design Systems Inc.

  0 cites
• US124132132025

  Efficient Clocking Structures for High-speed Systems Using Hybrid Digital Delay Lanes

  Cadence Design Systems, Inc.

  0 cites
• US122056732025

  Read Data Strobe Path Having Variation Compensation and Delay Lines

  Cadence Design Systems, Inc.

  0 cites
• US121842862024

  Clock Duty Cycle Measurement

  Cadence Design Systems, Inc.

  0 cites
• US120814072024

  Updating Configuration Settings of Network Elements When a Network Is Changed to a Planned Topology

  Ciena Corporation

  0 cites
• US118765212024

  Dynamically Updated Delay Line

  Cadence Design Systems, Inc.

  0 cites