Jianliang Shen

5 Patents

• US122673032025

  Input/output System Applied to Network Security Defense System

  PURPLE MOUNTAIN LABORATORIES

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• US121121152024

  Routing Structure and Method of Wafer Substrate with Standard Integration Zone for Integration On-wafer

  ZHEJIANG LAB

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• US118879642024

  Wafer-level Heterogeneous Dies Integration Structure and Method

  ZHEJIANG LAB

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• US118760712024

  System-on-wafer Structure and Fabrication Method

  ZHEJIANG LAB

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• US115702022023

  Method, Device and Ethernet Switch for Automatically Sensing Attack Behaviors

  THE PLA INFORMATION ENGINEERING UNIVERSITY

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