5 Patents
- US125124112025Wafer-level ASIC 3D Integrated Substrate, Packaging Device and Preparation Method
SJ Semiconductor(jiangyin) Corporation
0 cites - US124827592025Wafer-level ASIC 3D Integrated Substrate, Packaging Device and Preparation Method
SJ Semiconductor(jiangyin) Corporation
0 cites - US121989422025Packaging Structure and Method for Preparing Same
SJ Semiconductor(jiangyin) Corporation
0 cites - US117285582023Semiconductor Structure Including Antenna0 cites
- US116998402023Antenna Package Structure and Antenna Packaging Method
SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
0 cites