Jan Langer

9 Patents

• US125361322026

  Data Processing Engine Tile Architecture for an Integrated Circuit

  XILINX, Inc.

  0 cites
• US121056672024

  Device with Data Processing Engine Array That Enables Partial Reconfiguration

  XILINX, Inc.

  0 cites
• US119721322024

  Data Processing Engine Arrangement in a Device

  Xilinx, Inc.

  0 cites
• US118532352023

  Communicating Between Data Processing Engines Using Shared Memory

  XILINX, Inc.

  0 cites
• US117303252023

  Dual Mode Interconnect

  XILINX, Inc.

  0 cites
• US116694642023

  Multi-addressing Mode for DMA and Non-sequential Read and Write Patterns

  XILINX, Inc.

  0 cites
• US115994982023

  Device with Data Processing Engine Array That Enables Partial Reconfiguration

  XILINX, Inc.

  0 cites
• US115737262023

  Data Processing Engine Arrangement in a Device

  Xilinx, Inc.

  0 cites
• US115678812023

  Event-based Debug, Trace, and Profile in Device with Data Processing Engine Array

  XILINX, Inc.

  0 cites