Patents/Inventors

Jack T. Kavalieros

Portland, ORUS90 patents

95 Patents

US126105842026
Selective Growth of High-k Oxide on Channel of Gate-all-around Transistors
Intel Corporation
0 cites
US125751842026
CMOS Architecture with Thermally Stable Silicide Gate Workfunction Metal
Intel Corporation
0 cites
US125686442026
Contact Over Active Gate Structures with Trench Contact Layers for Advanced Integrated Circuit Structure Fabrication
Intel Corporation
0 cites
US125573402026
Cladding and Condensation for Strained Semiconductor Nanoribbons
Intel Corporation
0 cites
US125573522026
Forksheet Transistor Device with Air Gap Spine
Intel Corporation
0 cites
US125503732026
Selective Removal of Channel Bodies in Stacked Gate-all-around (GAA) Device Structures
INTEL CORPORATION
0 cites
US125504012026
Doped STI to Reduce Source/drain Diffusion for Germanium NMOS Transistors
Intel Corporation
0 cites
US125433492026
Transistors with Ferroelectric Gates
Intel Corporation
0 cites
US125433512026
Enriched Semiconductor Nanoribbons for Producing Intrinsic Compressive Strain
INTEL CORPORATION
0 cites
US125384702026
Structures and Methods for Memory Cells
Intel Corporation
0 cites
US125385162026
Forksheet Transistor with Asymmetric Dielectric Spine
INTEL CORPORATION
0 cites
US125325262026
Metallic Sealants in Transistor Arrangements
Intel Corporation
0 cites
US125139582025
Nanowire Transistor Fabrication with Hardmask Layers
Sony Group Corporation
0 cites
US124396592025
Gate-all-around Integrated Circuit Structures Having Germanium-diffused Nanoribbon Channel Structures
Intel Corporation
0 cites
US124330072025
Transistor Gate Trench Engineering to Decrease Capacitance and Resistance
Intel Corporation
0 cites
US124262472025
Capacitor Connections in Dielectric Layers
Intel Corporation
0 cites
US124143392025
Formation of Gate Spacers for Strained PMOS Gate-all-around Transistor Structures
Intel Corporation
0 cites
US123763622025
Field Effect Transistors with a Gated Oxide Semiconductor Source/drain Spacer
Intel Corporation
0 cites
US123426142025
Asymmetric Gate Structures and Contacts for Stacked Transistors
Intel Corporation
0 cites
US122888032025
Transistor with Isolation Below Source and Drain
Intel Corporation
0 cites
US122552342025
Integrated Circuit Structures Having Germanium-based Channels
Intel Corporation
0 cites
US122438752025
Forksheet Transistors with Dielectric or Conductive Spine
Intel Corporation
0 cites
US122389132025
Two Transistor Memory Cell Using Stacked Thin-film Transistors
Intel Corporation
0 cites
US122242022025
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US121991422025
Neighboring Gate-all-around Integrated Circuit Structures Having Conductive Contact Stressor Between Epitaxial Source or Drain Regions
Intel Corporation
0 cites
US121913492025
Reducing Off-state Leakage in Semiconductor Devices
Intel Corporation
0 cites
US121913952025
Dual Gate Control for Trench Shaped Thin Film Transistors
Intel Corporation
0 cites
US121838312024
Self-aligned Contacts for Thin Film Transistors
Intel Corporation
0 cites
US121762842024
Through Plate Interconnect for a Vertical MIM Capacitor
Intel Corporation
0 cites
US121426892024
Transistor Including Wrap Around Source and Drain Contacts
Intel Corporation
0 cites
US121259172024
Thin Film Transistors Having Double Gates
Intel Corporation
0 cites
US121193872024
Low Resistance Approaches for Fabricating Contacts and the Resulting Structures
Intel Corporation
0 cites
US120877502024
Stacked-substrate FPGA Semiconductor Devices
Intel Corporation
0 cites
US120806432024
Integrated Circuit Structures Having Differentiated Interconnect Lines in a Same Dielectric Layer
Intel Corporation
0 cites
US120682062024
Extension of Nanocomb Transistor Arrangements to Implement Gate All Around
Intel Corporation
0 cites
US120683192024
High Performance Semiconductor Oxide Material Channel Regions for NMOS
Intel Corporation
0 cites
US120466372024
Nanowire Transistor Fabrication with Hardmask Layers
Sony Group Corporation
0 cites
US120209292024
Epitaxial Layer with Substantially Parallel Sides
Intel Corporation
0 cites
US119964112024
Stacked Forksheet Transistors
Intel Corporation
0 cites
US119964472024
Field Effect Transistors with Gate Electrode Self-aligned to Semiconductor Fin
Intel Corporation
0 cites
US119978472024
Thin Film Transistors with Spacer Controlled Gate Length
Intel Corporation
0 cites
US119918732024
Capacitor Separations in Dielectric Layers
Intel Corporation
0 cites
US119787992024
Method for Fabricating Transistor with Thinned Channel
Tahoe Research, Ltd.
0 cites
US119788042024
Recessed Thin-channel Thin-film Transistor
Intel Corporation
0 cites
US119800372024
Memory Cells with Ferroelectric Capacitors Separate from Transistor Gate Stacks
Intel Corporation
0 cites
US119294352024
Ferroelectric Gate Stack for Band-to-band Tunneling Reduction
Intel Corporation
0 cites
US119233702024
Forksheet Transistors with Dielectric or Conductive Spine
Intel Corporation
0 cites
US119232902024
Halogen Treatment for NMOS Contact Resistance Improvement
Intel Corporation
0 cites
US119234102024
Transistor with Isolation Below Source and Drain
Intel Corporation
0 cites
US119234212024
Integrated Circuit Structures Having Germanium-based Channels
Intel Corporation
0 cites
US119014002024
MFM Capacitor and Process for Forming Such
Intel Corporation
0 cites
US118943722024
Stacked Trigate Transistors with Dielectric Isolation and Process for Forming Such
Intel Corporation
0 cites
US118944652024
Deep Gate-all-around Semiconductor Device Having Germanium or Group III-V Active Layer
Google LLC
0 cites
US118698902024
Stacked Transistors with Contact Last
Intel Corporation
0 cites
US118627282024
Dual Gate Control for Trench Shaped Thin Film Transistors
Intel Corporation
0 cites
US118627302024
Top-gate Doped Thin Film Transistor
Intel Corporation
0 cites
US118376482023
Stacked Thin Film Transistors with Nanowires
Intel Corporation
0 cites
US118309332023
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
Intel Corporation
0 cites
US118324382023
Capacitor Connections in Dielectric Layers
Intel Corporation
0 cites
US117842392023
Subfin Leakage Suppression Using Fixed Charge
Intel Corporation
0 cites
US117770132023
Channel Formation for Three Dimensional Transistors
Intel Corporation
0 cites
US117697892023
MFM Capacitor with Multilayered Oxides and Metals and Processes for Forming Such
Intel Corporation
0 cites
US117641042023
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US117642752023
Indium-containing Fin of a Transistor Device with an Indium-rich Core
Intel Corporation
0 cites
US117642822023
Antiferroelectric Gate Dielectric Transistors and Their Methods of Fabrication
Intel Corporation
0 cites
US117643032023
Thin Film Transistors Having Double Gates
Intel Corporation
0 cites
US117424072023
Multilayer High-k Gate Dielectric for a High Performance Logic Transistor
Intel Corporation
0 cites
US117424292023
Thin-film Transistors with Low Contact Resistance
Intel Corporation
0 cites
US117356702023
Non-selective Epitaxial Source/drain Deposition to Reduce Dopant Diffusion for Germanium NMOS Transistors
Intel Corporation
0 cites
US117272602023
Applications of Back-end-of-line (BEOL) Capacitors in Compute-in-memory (CIM) Circuits
Intel Corporation
0 cites
US117217352023
Thin Film Transistors Having U-shaped Features
Intel Corporation
0 cites
US116997562023
Source/drain Diffusion Barrier for Germanium Nmos Transistors
Intel Corporation
0 cites
US116950512023
Gate Stacks for Finfet Transistors
Intel Corporation
0 cites
US116902152023
Self-aligned Bitline and Capacitor via Formation
Intel Corporation
0 cites
US116839292023
Method for Making Memory Cells Based on Thin-film Transistors
Intel Corporation
0 cites
US116769662023
Stacked Transistors Having Device Strata with Different Channel Widths
Intel Corporation
0 cites
US116770032023
Nanowire Transistor Fabrication with Hardmask Layers
Sony Group Corporation
0 cites
US116706822023
FINFET Transistor Having a Doped Sub Fin Structure to Reduce Channel to Substrate Leakage
Tahoe Research, Ltd.
0 cites
US116582222023
Thin Film Transistor with Charge Trap Layer
Intel Corporation
0 cites
US116520472023
Intermediate Separation Layers at the Back-end-of-line
Intel Corporation
0 cites
US116526062023
Advanced Encryption Standard Semiconductor Devices Fabricated on a Stacked-substrate
Intel Corporation
0 cites
US116409612023
III-V Source/drain in Top NMOS Transistors for Low Temperature Stacked Transistor Contacts
Intel Corporation
0 cites
US116371852023
Contact Stacks to Reduce Hydrogen in Semiconductor Devices
Intel Corporation
0 cites
US116317372023
Ingaas Epi Structure and Wet Etch Process for Enabling Iii-v GAA in Art Trench
Intel Corporation
0 cites
US116264372023
Integration of Metasurface Lens on Wafer Level Substrate
Intel Corporation
0 cites
US116264752023
Trench Capacitor with Extended Dielectric Layer
Intel Corporation
0 cites
US116265192023
Fabrication of Non-planar IGZO Devices for Improved Electrostatics
Intel Corporation
0 cites
US116108942023
Capacitor Separations in Dielectric Layers
Intel Corporation
0 cites
US116055652023
Three Dimensional Integrated Circuits with Stacked Transistors
Intel Corporation
0 cites
US115945332023
Stacked Trigate Transistors with Dielectric Isolation Between First and Second Semiconductor Fins
Intel Corporation
0 cites
US115881022023
Semiconductor Material for Resistive Random Access Memory
Intel Corporation
0 cites
US115750052023
Asymmetrical Semiconductor Nanowire Field-effect Transistor
Intel Corporation
0 cites
US115692332023
Techniques and Mechanisms for Operation of Stacked Transistors
Intel Corporation
0 cites
US115692432023
Stacked-substrate DRAM Semiconductor Devices
Intel Corporation
0 cites
US115631192023
Etchstop Regions in Fins of Semiconductor Devices
Intel Corporation
0 cites