Igor Keller

3 Patents

• US125968612026

  Efficient Delay Calculations in Replicated Designs

  Cadence Design Systems, Inc.

  0 cites
• US120865292024

  Circuit Design Modification Using Timing-based Yield Calculation

  Cadence Design Systems, Inc.

  0 cites
• US117757192023

  Cell Instance Charge Model for Delay Calculation

  Cadence Design Systems, Inc.

  0 cites