Patents/Inventors

Hui Jae Yoo

Hillsboro, ORUS54 patents

45 Patents

US126160122026
Stacked Random Access Memory Devices with Multilayer Continuous Vias
Intel Corporation
0 cites
US126044792026
Two Transistor Capacitorless Memory Cell with Stacked Thin-film Transistors
Intel Corporation
0 cites
US125990322026
Bilayer Memory Stacking with Lines Shared Between Bottom and Top Memory Layers
Intel Corporation
0 cites
US125818572026
Integrated Thermoelectric Device to Mitigate Integrated Circuit Hot Spots
Intel Corporation
0 cites
US124827442025
Subtractively Patterned Interconnect Structures for Integrated Circuits
Intel Corporation
0 cites
US124069562025
Bilayer Memory Stacking with Computer Logic Circuits Shared Between Bottom and Top Memory Layers
Intel Corporation
0 cites
US123961552025
Backend Memory with Air Gaps in Upper Metal Layers
Intel Corporation
0 cites
US123763422025
Passivation Layers for Thin Film Transistors
Intel Corporation
0 cites
US123100322025
Stacked Backend Memory with Resistive Switching Devices
Intel Corporation
0 cites
US123005372025
Conformal Low Temperature Hermetic Dielectric Diffusion Barriers
Intel Corporation
0 cites
US122665682025
Interconnect Wires Including Relatively Low Resistivity Cores
Intel Corporation
0 cites
US122551372025
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US122242022025
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US121488062024
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US121502972024
Thin Film Transistors Having a Backside Channel Contact for High Density Memory
Intel Corporation
0 cites
US121487342024
Transistors, Memory Cells, and Arrangements Thereof
Intel Corporation
0 cites
US120806052024
Backside Contacts for Semiconductor Devices
Intel Corporation
0 cites
US120807812024
Fabrication of Thin Film Fin Transistor Structure
Intel Corporation
0 cites
US120402262024
Conformal Low Temperature Hermetic Dielectric Diffusion Barriers
Intel Corporation
0 cites
US120274582024
Subtractively Patterned Interconnect Structures for Integrated Circuits
Intel Corporation
0 cites
US120209292024
Epitaxial Layer with Substantially Parallel Sides
Intel Corporation
0 cites
US120027542024
Multi-height and Multi-width Interconnect Line Metallization for Integrated Circuit Structures
Intel Corporation
0 cites
US119964112024
Stacked Forksheet Transistors
Intel Corporation
0 cites
US119555602024
Passivation Layers for Thin Film Transistors and Methods of Fabrication
Intel Corporation
0 cites
US119424162024
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US119161182024
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US118814322024
Interconnect Wires Including Relatively Low Resistivity Cores
0 cites
US118698942024
Metallization Structures for Stacked Device Connectivity and Their Methods of Fabrication
Intel Corporation
0 cites
US118125992023
Compute Near Memory with Backend Memory
Intel Corporation
0 cites
US117988382023
Capacitance Reduction for Semiconductor Devices Based on Wafer Bonding
Intel Corporation
0 cites
US117698142023
Device Including Air Gapping of Gate Spacers and Other Dielectrics and Process for Providing Such
Intel Corporation
0 cites
US117642632023
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approaches
Intel Corporation
0 cites
US117641042023
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US116996812023
Multi-chip Module Having a Stacked Logic Chip and Memory Stack
Intel Corporation
0 cites
US116721332023
Vertically Stacked Memory Elements with Air Gap
Intel Corporation
0 cites
US116705452023
Conformal Low Temperature Hermetic Dielectric Diffusion Barriers
Intel Corporation
0 cites
US116463522023
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US116409612023
III-V Source/drain in Top NMOS Transistors for Low Temperature Stacked Transistor Contacts
Intel Corporation
0 cites
US116055652023
Three Dimensional Integrated Circuits with Stacked Transistors
Intel Corporation
0 cites
US116055922023
Method to Fabricate Metal and Ferromagnetic Metal Multilayer Interconnect Line for Skin Effect Suppression
Intel Corporation
0 cites
US115946732023
Two Terminal Spin Orbit Memory Devices and Methods of Fabrication
Intel Corporation
0 cites
US115878272023
Conformal Low Temperature Hermetic Dielectric Diffusion Barriers
Intel Corporation
0 cites
US115749102023
Device with Air-gaps to Reduce Coupling Capacitance and Process for Forming Such
Intel Corporation
0 cites
US115692382023
Vertical Memory Cells
Intel Corporation
0 cites
US115691262023
Interconnect Wires Including Relatively Low Resistivity Cores
Intel Corporation
0 cites