Hsien-chin Lin

3 Patents

• US123745422025

  Cut Metal Gate Process for Reducing Transistor Spacing

  TAIWAN SEMICONDUCTOR MANUFACTURING CO., Ltd.

  0 cites
• US119488422024

  Etch Stop Layer Between Substrate and Isolation Structure

  TAIWAN SEMICONDUCTOR MANUFACTURING CO., Ltd.

  0 cites
• US117215442023

  Cut Metal Gate Process for Reducing Transistor Spacing

  TAIWAN SEMICONDUCTOR MANUFACTURING CO., Ltd.

  0 cites