13 Patents
- US126160522026Methods and Apparatus to Reduce Defects in Interconnects Between Semicondcutor Dies and Package Substrates
Intel Corporation
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- US123411172025Methods and Apparatus to Reduce Defects in Interconnects Between Semiconductor Dies and Package Substrates
Intel Corporation
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- US120339302024Selectively Roughened Copper Architectures for Low Insertion Loss Conductive Features
Intel Corporation
0 cites - US119554482024Architecture to Manage FLI Bump Height Delta and Reliability Needs for Mixed EMIB Pitches
Intel Corporation
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- US116409342023Lithographically Defined Vertical Interconnect Access (VIA) in Dielectric Pockets in a Package Substrate
Intel Corporation
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