20 Patents
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- US124777982025Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
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0 cites - US124179122025Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
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0 cites - US123225942025Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
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0 cites - US123082292025Method for Making Memory Device Including a Superlattice Gettering Layer
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0 cites - US121991802025Semiconductor Device Including a Superlattice and an Asymmetric Channel and Related Methods
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0 cites - US121426412024Method for Making Gate-all-around (GAA) Device Including a Superlattice
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0 cites - US121193802024Method for Making Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
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0 cites - US120464702024Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
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0 cites - US120209262024Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
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0 cites - US120149232024Methods for Making Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
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- US119234182024Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
ATOMERA INCORPORATED
0 cites - US118699682024Semiconductor Device Including a Superlattice and an Asymmetric Channel and Related Methods
ATOMERA INCORPORATED
0 cites - US118483562023Method for Making Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
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0 cites - US118376342023Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
ATOMERA INCORPORATED
0 cites - US118107842023Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
ATOMERA INCORPORATED
0 cites - US117422022023Methods for Making Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
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0 cites - US115693682023Method for Making Semiconductor Device Including a Superlattice and Providing Reduced Gate Leakage
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