Harold Pilo

11 Patents

• US125121512025

  Memory with Hybrid Write Assist Scheme

  Synopsys, Inc.

  0 cites
• US123619902025

  Memory with External Clock Synchronized Operation

  Synopsys, Inc.

  0 cites
• US123408642025

  Interface Level-shifter Dual-rail Memory Architecture

  Synopsys, Inc.

  0 cites
• US123408652025

  Reduced Circuit Area Memory Device with a Half-word Memory Architecture

  Synopsys, Inc.

  0 cites
• US123080912025

  Pseudo-2-port Memory with Dual Pre-charge Circuits

  Synopsys, Inc.

  0 cites
• US122435812025

  Output Driver Level-shifting Latch Circuit for Dual-rail Memory

  Synopsys, Inc.

  0 cites
• US121657382024

  SRAM Non-clamping Write Driver with Write Assist

  SYNOPSYS, Inc.

  0 cites
• US121484902024

  At-speed Synchronous Write-through Operation for Testing Two-port Memory

  Synopsys, Inc.

  0 cites
• US121128182024

  Scan Chain Compression for Testing Memory of a System on a Chip

  Synopsys, Inc.

  0 cites
• US120945132024

  Power Supply Tracking Circuitry for Embedded Memories

  Synopsys, Inc.

  0 cites
• US120738762024

  Memory Clock Level-shifting Buffer with Extended Range

  Synopsys, Inc.

  0 cites