84 Patents
- US125987342026Method of Making 3D Memory Stacking Formation with High Circuit Density
Tokyo Electron Limited
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- US1253852020263D High Density Self-aligned Nanosheet Device Formation with Efficient Layout and Design
Tokyo Electron Limited
0 cites - US125299652026Method for Selective Exposure of Wafer to Corrective Irradiation at a Per-die Level
Tokyo Electron Limited
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- US1250744720253D Advanced Transistor Architecture Integrated with Source/drain Spider Design
Tokyo Electron Limited
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- US1250160220253D Hybrid Memory Using Horizontally Oriented Conductive Dielectric Channel Regions
Tokyo Electron Limited
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- US124647042025Three-dimensional Plurality of N Horizontal Memory Cells with Enhanced High Performance Circuit Density
Tokyo Electron Limited
0 cites - US124555112025In-situ Lithography Pattern Enhancement with Localized Stress Treatment Tuning Using Heat Zones
Tokyo Electron Limited
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- US124396412025Compact 3D Design and Connections with Optimum 3D Transistor Stacking
Tokyo Electron Limited
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- US1238111820253D Multiple Location Compressing Bonded Arm for Advanced Integration
Tokyo Electron Limited
0 cites - US1236395620252D Material to Integrate 3D Horizontal Nanosheets Using a Carrier Nanosheet
Tokyo Electron Limited
0 cites - US123567062025Methods for Forming High Performance Three Dimensionally Stacked Transistors Based on Dielectric Nano Sheets
Tokyo Electron Limited
0 cites - US123494242025Epitaxial Semiconductor 3D Horizontal Nano Sheet with High Mobility 2D Material Channel
Tokyo Electron Limited
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- US123426032025Plurality of Devices in Adjacent 3D Stacks in Different Circuit Locations
Tokyo Electron Limited
0 cites - US123362702025High Performance New Channel Materials Precision Aligned 3D CFET Device Architecture
Tokyo Electron Limited
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- US1231757720253D Semiconductor Device with 2D Semiconductor Material and Method of Forming the Same
Tokyo Electron Limited
0 cites - US123026062025Semiconductor Devices with Crystallized Channel Regions and Methods of Manufacturing Thereof
Tokyo Electron Limited
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- US1227269220253D Selective Material Transformation to Integrate 2D Material Elements
Tokyo Electron Limited
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- US1224965920252D Materials with Inverted Gate Electrode for High Density 3D Stacking
Tokyo Electron Limited
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- US122180112025Method of Making 3D Segmented Devices for Enhanced 3D Circuit Density
Tokyo Electron Limited
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- US122182442025Vertical Transistor Structures and Methods Utilizing Selective Formation
TOKYO ELECTRON LIMITED
0 cites - US121912102025Formation of High Density 3D Circuits with Enhanced 3D Conductivity
Tokyo Electron Limited
0 cites - US1217624920243D Nano Sheet Method Using 2D Material Integrated with Conductive Oxide for High Performance Devices
TOKYO ELECTRON LIMITED
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- US121486682024Stackable Semiconductor Device with 2D Material Layer and Methods of Manufacturing Thereof
Tokyo Electron Limited
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- US1213338720243D Memory with Conductive Dielectric Channel Integrated with Logic Access Transistors
Tokyo Electron Limited
0 cites - US121144802024Method of Making of Plurality of 3D Vertical Logic Elements Integrated with 3D Memory
Tokyo Electron Limited
0 cites - US120876402024High Density Logic Formation Using Multi-dimensional Laser Annealing
Tokyo Electron Limited
0 cites - US120878172024High Performance 3D Vertical Transistor Device Enhancement Design
Tokyo Electron Limited
0 cites - US1206820520243D High Density Compact Metal First Approach for Hybrid Transistor Designs Without Using Epitaxial Growth
TOKYO ELECTRON LIMITED
0 cites - US1204023620243D Devices with 3D Diffusion Breaks and Method of Forming the Same
Tokyo Electron Limited
0 cites - US120209902024Method for Threshold Voltage Tuning Through Selective Deposition of High-k Metal Gate (HKMG) Film Stacks
Tokyo Electron Limited
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- US120011472024Precision Multi-axis Photolithography Alignment Correction Using Stressor Film
Tokyo Electron Limited
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- US119787352024Transistor Stack of Vertical Channel Ferroelectric Fets and Methods of Forming the Transistor Stack
Tokyo Electron Limited
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- US119087472024Method for Designing Three Dimensional Metal Lines for Enhanced Device Performance
Tokyo Electron Limited
0 cites - US118943782024Multiple Nano Layer Transistor Layers with Different Transistor Architectures for Improved Circuit Layout and Performance
Tokyo Electron Limited
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- US118761252024Method of Making a Plurality of High Density Logic Elements with Advanced CMOS Device Layout
Tokyo Electron Limited
0 cites - US118624972024Method for Die-level Unique Authentication and Serialization of Semiconductor Devices Using Electrical and Optical Marking
Tokyo Electron Limited
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- US118308762023Three-dimensional Device with Self-aligned Vertical Interconnection
Tokyo Electron Limited
0 cites - US118108542023Multi-dimensional Vertical Switching Connections for Connecting Circuit Elements
Tokyo Electron Limited
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- US117770152023Multiple Planes of Transistors with Different Transistor Architectures to Enhance 3D Logic and Memory Circuits
Tokyo Electron Limited
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- US117642002023High Density Architecture Design for 3D Logic and 3D Memory Circuits
Tokyo Electron Limited
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- US117215822023Method of Making 3D Circuits with Integrated Stacked 3D Metal Lines for High Density Circuits
Tokyo Electron Limited
0 cites - US117215922023Method of Making Vertical Semiconductor Nanosheets with Diffusion Breaks
Tokyo Electron Limited
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- US116950582023Method of Expanding 3D Device Architectural Designs for Enhanced Performance
Tokyo Electron Limited
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- US116409372023Horizontal Programmable Conducting Bridges Between Conductive Lines
Tokyo Electron Limited
0 cites - US1163167120233D Complementary Metal Oxide Semiconductor (CMOS) Device and Method of Forming the Same
Tokyo Electron Limited
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- US1161099320233D Semiconductor Apparatus Manufactured with a Plurality of Substrates and Method of Manufacture Thereof
Tokyo Electron Limited
0 cites - US115945352023High Performance Nanosheet Fabrication Method with Enhanced High Mobility Channel Elements
Tokyo Electron Limited
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- US115576552023Device and Method of Forming with Three-dimensional Memory and Three-dimensional Logic
Tokyo Electron Limited
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- US115520802023Method of Making Multiple Nano Layer Transistors to Enhance a Multiple Stack CFET Performance
Tokyo Electron Limited
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