Patents/Inventors

Guillaume Bouche

Portland, ORUS17 patents

17 Patents

US125124072025
Stitching to Enable Dense Interconnect Arrangements
Intel NDTM US LLC
0 cites
US125060762025
Power Rail Between Fins of a Transistor Structure
Intel Corporation
0 cites
US124396592025
Gate-all-around Integrated Circuit Structures Having Germanium-diffused Nanoribbon Channel Structures
Intel Corporation
0 cites
US123763532025
Source/drain Regions in Integrated Circuit Structures
Intel Corporation
0 cites
US123289362025
Gate Spacing in Integrated Circuit Structures
Intel Corporation
0 cites
US123158052025
Self-aligned Lateral Contacts
INTEL CORPORATION
0 cites
US122373882025
Transistor Arrangements with Stacked Trench Contacts and Gate Straps
Intel Corporation
0 cites
US122117862025
Stacked Vias with Bottom Portions Formed Using Selective Growth
Intel Corporation
0 cites
US122118982025
Device Contact Sizing in Integrated Circuit Structures
Intel Corporation
0 cites
US121487512024
Use of a Placeholder for Backside Contact Formation for Transistor Arrangements
Intel Corporation
0 cites
US121425162024
Self Aligned Buried Power Rail
GLOBALFOUNDRIES U.S. Inc.
0 cites
US120948222024
Buried Power Rails with Self-aligned Vias to Trench Contacts
Intel Corporation
0 cites
US119844872024
Non-planar Transistor Arrangements with Asymmetric Gate Enclosures
Intel Corporation
0 cites
US119731212024
Device Contacts in Integrated Circuit Structures
Intel Corporation
0 cites
US119160102024
Back End of Line Integration for Self-aligned Vias
Intel Corporation
0 cites
US119161062024
Source/drain Regions in Integrated Circuit Structures
Intel Corporation
0 cites
US117497152023
Isolation Regions in Integrated Circuit Structures
Intel Corporation
0 cites