Patents/Inventors

Guei-yuan Lueh

San Jose, CAUS32 patents

28 Patents

US125790122026
Forward Progress Guarantee Using Single-level Synchronization at Individual Thread Granularity
INTEL CORPORATION
0 cites
US125729972026
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US125360182026
Method and Apparatus for Performing Reduction Operations on a Plurality of Associated Data Element Values
Intel Corporation
0 cites
US124939222025
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US124749412025
Kernel Source Adaptation for Execution on a Graphics Processing Unit
Intel Corporation
0 cites
US123997342025
Engine to Enable High Speed Context Switching via On-die Storage
INTEL CORPORATION
0 cites
US123866172025
Gathering Payload from Arbitrary Registers for Send Messages in a Graphics Environment
INTEL CORPORATION
0 cites
US123466942025
Register File for Systolic Array
Intel Corporation
0 cites
US123333062025
High Performance Constant Cache and Constant Access Mechanisms
Intel Corporation
0 cites
US122109052025
Multiple Register Allocation Sizes for Threads
INTEL CORPORATION
0 cites
US121901182025
Data Locality Enhancement for Graphics Processing Units
INTEL CORPORATION
0 cites
US121747832024
Systolic Array of Arbitrary Physical and Logical Depth
Intel Corporation
0 cites
US121644302024
Instruction Prefetch Mechanism
INTEL CORPORATION
0 cites
US121314022024
Page Faulting and Selective Preemption
Intel Corporation
0 cites
US120676412024
Page Faulting and Selective Preemption
Intel Corporation
0 cites
US120079352024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119540632024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119005022024
Compiler Assisted Register File Write Reduction
Intel Corporation
0 cites
US118868752024
Systems and Methods for Performing Nibble-sized Operations on Matrix Elements
Intel Corporation
0 cites
US118617612024
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US118034762023
Instruction Prefetch Mechanism
INTEL CORPORATION
0 cites
US117626962023
Hybrid Low Power Homogenous Grapics Processing Units
INTEL CORPORATION
0 cites
US117483022023
Engine to Enable High Speed Context Switching via On-die Storage
INTEL CORPORATION
0 cites
US117267932023
Data Locality Enhancement for Graphics Processing Units
INTEL CORPORATION
0 cites
US117097932023
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US116693292023
Instructions and Logic for Vector Multiply Add with Zero Skipping
Intel Corporation
0 cites
US116402972023
Instruction and Logic for Systolic Dot Product with Accumulate
Intel Corporation
0 cites
US115798782023
Register Sharing Mechanism to Equally Allocate Disabled Thread Registers to Active Threads
Intel Corporation
0 cites