Patents/Inventors

George Vergis

Portland, ORUS45 patents

34 Patents

US126031152026
Method and Apparatus to Perform Training on a Data Bus Between a Dynamic Random Access Memory (DRAM) and a Data Buffer on a Buffered Dual In-line Memory Module
Intel Corporation
0 cites
US125881492026
GDDR Memory Expander Using CMT Connector
Intel Corporation
0 cites
US125737952026
Pin Configuration for Device-to-device Connection
Intel Corporation
0 cites
US125493312026
Memory Bus Integrity and Data Encryption (IDE)
Intel Corporation
0 cites
US125432872026
High-capacity Server Memory Device in a Single Unit Form Factor
Intel Corporation
0 cites
US125310982026
Memory Module Based Data Buffer Communication Bus Training
Intel Corporation
0 cites
US124954972025
Low Power Memory Module
Intel Corporation
0 cites
US124815462025
Self-healing Low Speed Serial Interface
Intel Corporation
0 cites
US123328122025
Memory Device Manageability Bus
Intel Corporation
0 cites
US123346742025
DIMM Retention Assembly for Compression Mount Technology and Land Grid Array Connector Loading
Intel Corporation
0 cites
US123155872025
DIMM Socket with Seating Floor to Meet Both Longer Length Edge Contacts and Shorter Length Edge Contacts
Intel Corporation
0 cites
US123155882025
Method and Apparatus for Improved Memory Module Supply Current Surge Response
Intel Corporation
0 cites
US123009312025
Dual In-line Memory Module (DIMM) Socket That Prevents Improper DIMM Release
Intel Corporation
0 cites
US122941672025
Closed Loop Compressed Connector Pin
Intel Corporation
0 cites
US122679572025
Hybrid Pitch Through Hole Connector
Intel Corporation
0 cites
US122376202025
Device-to-device Connection with Multiple Parallel Ground Pins
Intel Corporation
0 cites
US121476982024
High Performance Memory Module with Reduced Loading
Intel Corporation
0 cites
US121441102024
Reduced Vertical Profile Ejector for Liquid Cooled Modules
Intel Corporation
0 cites
US121068182024
Power Control of a Memory Device in Connected Standby State
Intel Corporation
0 cites
US120873522024
Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate
Tahoe Research, Ltd.
0 cites
US120693292024
Dynamic Linking of Codesets in Universal Remote Control Devices
Universal Electronics Inc.
0 cites
US120405682024
Connector with Staggered Pin Orientation
Intel Corporation
0 cites
US119846852024
Retention Latch with Spring Mechanism
Intel Corporation
0 cites
US119613912024
Codeset Communication Format and Related Methods and Structures
Universal Electronics Inc.
0 cites
US119280422024
Initialization and Power Fail Isolation of a Memory Module in a System
Intel Corporation
0 cites
US119216522024
Method, Apparatus and System for Device Transparent Grouping of Devices on a Bus
Intel Corporation
0 cites
US117898802023
Load Reduced Nonvolatile Memory Interface
SK Hynix NAND Product Solutions Corp.
0 cites
US117924662023
Dynamic Linking of Codesets in Universal Remote Control Devices
Universal Electronics Inc.
0 cites
US117766192023
Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate
Tahoe Research, Ltd.
0 cites
US116577032023
Codeset Communication Format and Related Methods and Structures
Universal Electronics Inc.
0 cites
US115875972023
Connector Retention Mechanism for Improved Structural Reliability
Intel Corporation
0 cites
US115882792023
Dual In-line Memory Module (DIMM) Socket Circuit to Detect Improper Insertion of a DIMM Edge Into a DIMM Socket
Intel Corporation
0 cites
US115891032023
Dynamic Linking of Codesets in Universal Remote Control Devices
Universal Electronics Inc.
0 cites
US115573332023
Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate
Tahoe Research, Ltd.
0 cites