Geert Van Der Plas

4 Patents

• US121548302024

  Method of Producing a Gate Cut in a Semiconductor Component

  IMEC Vzw

  0 cites
• US118224752023

  Integrated Circuit with 3D Partitioning

  Imec Vzw

  0 cites
• US117570392023

  Method for Inducing Stress in Semiconductor Devices

  IMEC VZW

  0 cites
• US116212952023

  Bipolar Selector Device for a Memory Array

  IMEC Vzw

  0 cites