Frederic Revenu

3 Patents

• US117149502023

  Automated Timing Closure on Circuit Designs

  XILINX, Inc.

  0 cites
• US117095212023

  Synchronous Clock Domain Crossing Skew Optimization and Multi-clock Buffer (MBUFG)

  XILINX, Inc.

  0 cites
• US116818462023

  Sub-fpga Level Compilation Platform with Adjustable Dynamic Region for Emulation/prototyping Designs

  XILINX, Inc.

  0 cites