17 Patents
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- US125882622026Sacrificial Gate Capping Layer for Gate Protection During Source/drain Contact Opening
Tokyo Electron Limited
0 cites - US125686772026Method of Self-aligned Dielectric Wall Formation for Forksheet Application
Tokyo Electron Limited
0 cites - US125640272026Top-down Self-alignment of Vias in a Semiconductor Device for Sub-22nm Pitch Metals
Tokyo Electron Limited
0 cites - US125060052025Methods and Structures for Increasing Stability of Soft or Organic Features
Tokyo Electron Limited
0 cites - US124827022025Wet Etch Process and Methods to Form Air Gaps Between Metal Interconnects
Tokyo Electron Limited
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- US122372162025Method for Filling Recessed Features in Semiconductor Devices with a Low-resistivity Metal
Tokyo Electron Limited
0 cites - US121486242024Wet Etch Process and Method to Control Fin Height and Channel Area in a Fin Field Effect Transistor (finfet)
Tokyo Electron Limited
0 cites - US121005982024Methods for Planarizing a Substrate Using a Combined Wet Etch and Chemical Mechanical Polishing (CMP) Process
Tokyo Electron Limited
0 cites - US120092112024Method for Highly Anisotropic Etching of Titanium Oxide Spacer Using Selective Top-deposition
Tokyo Electron Limited
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- US116519652023Method and System for Capping of Cores for Self-aligned Multiple Patterning
Tokyo Electron Limited
0 cites - US115574792023Methods for EUV Inverse Patterning in Processing of Microelectronic Workpieces
TOKYO ELECTRON LIMITED
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