33 Patents
- US125751842026CMOS Architecture with Thermally Stable Silicide Gate Workfunction Metal
Intel Corporation
0 cites - US125016842025Integrated Circuit Structures with Backside Self-aligned Penetrating Conductive Source or Drain Contact
Intel Corporation
0 cites - US123425742025Contact Resistance Reduction in Transistor Devices with Metallization on Both Sides
Intel Corporation
0 cites - US122551372025Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites - US122306352025Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Selective Bottom-up Approach
Intel Corporation
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- US121070852024Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
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- US119424162024Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
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- US118943722024Stacked Trigate Transistors with Dielectric Isolation and Process for Forming Such
Intel Corporation
0 cites - US118626362024Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Selective Bottom-up Approach
Intel Corporation
0 cites - US118309332023Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
Intel Corporation
0 cites - US117988382023Capacitance Reduction for Semiconductor Devices Based on Wafer Bonding
Intel Corporation
0 cites - US117698142023Device Including Air Gapping of Gate Spacers and Other Dielectrics and Process for Providing Such
Intel Corporation
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- US117642632023Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approaches
Intel Corporation
0 cites - US117423462023Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites - US116769662023Stacked Transistors Having Device Strata with Different Channel Widths
Intel Corporation
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- US116160602023Techniques for Forming Gate Structures for Transistors Arranged in a Stacked Configuration on a Single Fin Structure
Intel Corporation
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- US115945332023Stacked Trigate Transistors with Dielectric Isolation Between First and Second Semiconductor Fins
Intel Corporation
0 cites - US115737982023Stacked Transistors with Different Gate Lengths in Different Device Strata
Intel Corporation
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- US115521042023Stacked Transistors with Dielectric Between Channels of Different Device Strata
Intel Corporation
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