Patents/Inventors

Duc Quang Bui

Grand Prairie, TXUS29 patents

29 Patents

US124989252025
Register File Structures Combining Vector and Scalar Data with Global and Local Accesses
Texas Instruments Incorporated
0 cites
US124557402025
System and Method to Control the Number of Active Vector Lanes in a Processor
TEXAS INSTRUMENTS INCORPORATED
0 cites
US124500092025
System and Method for Predication Handling
TEXAS INSTRUMENTS INCORPORATED
0 cites
US124500552025
Vector SIMD VLIW Data Path Architecture
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123866232025
Conditional Execution Specification of Instructions Using Conditional Extension Slots in the Same Execute Packet in a VLIW Processor
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123669062025
Controlling the Number of Powered Vector Lanes via a Register Field
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123415342025
Butterfly Network on Load Data Return
Texas Instruments Incorporated
0 cites
US122658272025
Forming Constant Extensions in the Same Execute Packet in a VLIW Processor
TEXAS INSTRUMENTS INCORPORATED
0 cites
US122170542025
Method of Storing Register Data Elements to Interleave with Data Elements of a Different Register, a Processor Thereof, and a System Thereof
TEXAS INSTRUMENTS INCORPORATED
0 cites
US121644382024
Tracking Streaming Engine Vector Predicates to Control Processor Execution
Texas Instruments Incorporated
0 cites
US121247282024
Quick Clearing of Registers
Texas Instruments Incorporated
0 cites
US121056352024
Method and Apparatus for Vector Permutation
TEXAS INSTRUMENTS INCORPORATED
0 cites
US120998432024
Streaming Address Generation
TEXAS INSTRUMENTS INCORPORATED
0 cites
US120860742024
Method and Apparatus for Permuting Streamed Data Elements
Texas Instruments Incorporated
0 cites
US120728122024
Highly Integrated Scalable, Flexible DSP Megamodule Architecture
Texas Instruments Incorporated
0 cites
US119890722024
Controlling the Number of Powered Vector Lanes via a Register Field
Texas Instruments Incorporated
0 cites
US119778872024
System and Method to Control the Number of Active Vector Lanes in a Processor
Texas Instruments Incorporated
0 cites
US119608922024
Conditional Execution Specification of Instructions Using Conditional Extension Slots in the Same Execute Packet in a VLIW Processor
Texas Instruments Incorporated
0 cites
US119221662024
Vector SIMD VLIW Data Path Architecture
Texas Instruments Incorporated
0 cites
US118364942023
System and Method for Addressing Data in Memory
Texas Instruments Incorporated
0 cites
US118048582023
Butterfly Network on Load Data Return
Texas Instruments Incorporated
0 cites
US117553222023
Vector Load and Duplicate Operations
Texas Instruments Incorporated
0 cites
US117482702023
Tracking Streaming Engine Vector Predicates to Control Processor Execution
Texas Instruments Incorporated
0 cites
US117040462023
Quick Clearing of Registers
Texas Instruments Incorporated
0 cites
US116815322023
Method for Forming Constant Extensions in the Same Execute Packet in a VLIW Processor
Texas Instruments Incorporated
0 cites
US116694632023
Method and Apparatus for Permuting Streamed Data Elements
Texas Instruments Incorporated
0 cites
US116046522023
Streaming Address Generation
Texas Instruments Incorporated
0 cites
US115563382023
Vector SIMD VLIW Data Path Architecture
Texas Instruments Incorporated
0 cites
US115505732023
System and Method to Control the Number of Active Vector Lanes in a Processor
Texas Instmments Incorporated
0 cites