Patents/Inventors

Dheeraj Subbareddy

Portland, ORUS39 patents

31 Patents

US126194342026
Programmable Fabric-based Instruction Set Architecture for a Processor
Altera Corporation
0 cites
US125990212026
Homogenous Die Stacking with Increased Element Density
Altera Corporation
0 cites
US124224772025
Segmented Row Repair for Programmable Logic Devices
Intel Corporation
0 cites
US123553592025
Switch Based on Load Current
Intel Corporation
0 cites
US123532382025
Flexible Instruction Set Architecture Supporting Varying Frequencies
Intel Corporation
0 cites
US123477832025
Interconnect Architecture with Silicon Interposer and EMIB
Intel Corporation
0 cites
US123415112025
Power Management Using Voltage Islands on Programmable Logic Devices
Altera Corporation
0 cites
US123344492025
Selective Use of Different Advanced Interface Bus with Electronic Chips
Altera Corporation
0 cites
US122943682025
Three-dimensional Stacked Programmable Logic Fabric and Processor Design Architecture
Intel Corporation
0 cites
US122731072025
Dynamically Scalable Timing and Power Models for Programmable Logic Devices
Altera Corporation
0 cites
US122666252025
Innovative Interconnect Design for Package Architecture to Improve Latency
Altera Corporation
0 cites
US122378312025
Network-on-chip (NOC) with Flexible Data Width
Intel Corporation
0 cites
US122161502025
On-die Aging Measurements for Dynamic Timing Modeling
Altera Corporation
0 cites
US122064102025
Programmable Logic Device with Fine-grained Disaggregation
Intel Corporation
0 cites
US121538662024
Modular Periphery Tile for Integrated Circuit Device
Altera Corporation
0 cites
US120260082024
Techniques for Clock Signal Transmission in Integrated Circuits and Interposers
Altera Corporation
0 cites
US120079292024
Low-latency Optical Connection for CXL for a Server CPU
Altera Corporation
0 cites
US119831352024
Electrical and Optical Interfaces at Different Heights Along an Edge of a Package to Increase Bandwidth Along the Edge
Intel Corporation
0 cites
US119293392024
Innovative Interconnect Design for Package Architecture to Improve Latency
Intel Corporation
0 cites
US119159962024
Microelectronics Assembly Including Top and Bottom Packages in Stacked Configuration with Shared Cooling
Intel Corporation
0 cites
US119012992024
Interconnect Architecture with Silicon Interposer and EMIB
Intel Corporation
0 cites
US117898832023
Inter-die Communication of Programmable Logic Devices
INTEL CORPORATION
0 cites
US117149412023
Modular Periphery Tile for Integrated Circuit Device
Intel Corporation
0 cites
US117000022023
Network-on-chip (NOC) with Flexible Data Width
Intel Corporation
0 cites
US116694722023
Frequency Translation Circuitry for an Interconnection in an Active Interposer of a Semiconductor Package
Intel Corporation
0 cites
US116581442023
Innovative Interconnect Design for Package Architecture to Improve Latency
Intel Corporation
0 cites
US116217132023
High-speed Core Interconnect for Multi-die Programmable Logic Devices
Intel Corporation
0 cites
US116092622023
On-die Aging Measurements for Dynamic Timing Modeling
Intel Corporation
0 cites
US116108562023
Connectivity Between Integrated Circuit Dice in a Multi-chip Package
Intel Corporation
0 cites
US115950452023
Programmable Logic Device with Fine-grained Disaggregation
Intel Corporation
0 cites
US115575412023
Interconnect Architecture with Silicon Interposer and EMIB
Intel Corporation
0 cites