Patents/Inventors

Deepyanti Taneja

Happy Valley, ORUS9 patents

4 Patents

US126219792026
Multi-tier Memory Structure with Graded Characteristics
INTEL CORPORATION
0 cites
US126220422026
Multi-layered or Graded Gate Dielectric in Thin Film Transistor (TFT) Structures
INTEL CORPORATION
0 cites
US126105822026
Multi-layered Source and Drain Contacts for a Thin Film Transistor (TFT) Structure
Intel Corporation
0 cites
US125124092025
Hybrid Etch Stop Layers
INTEL CORPORATION
0 cites