Patents/Inventors

Debendra Das Sharma

Saratoga, CAUS65 patents

65 Patents

US125917272026
Lane Repair and Lane Reversal Implementation for Die-to-die (D2D) Interconnects
Intel Corporation
0 cites
US125783842026
Unified Test and Debug Chiplet Architecture
Intel Corporation
0 cites
US125050652025
On-package Die-to-die (D2D) Interconnect for Memory Using Universal Chiplet Interconnect Express (ucie) PHY
Intel Corporation
0 cites
US124990192025
Retimers to Extend a Die-to-die Interconnect
Intel Corporation
0 cites
US124990742025
Die-to-die Interconnect Protocol Layer
Intel Corporation
0 cites
US125005832025
Clock Interpolation System for Eye-centering
INTEL CORPORATION
0 cites
US124816142025
Standard Interfaces for Die to Die (D2D) Interconnect Stacks
Intel Corporation
0 cites
US124685972025
Valid Signal for Latency Sensitive Die-to-die (D2D) Interconnects
Intel Corporation
0 cites
US124558272025
System, Apparatus and Methods for Performing Shared Memory Operations
Intel Corporation
0 cites
US124059042025
Sharing Memory and I/O Services Between Nodes
Intel Corporation
0 cites
US124059122025
Link Initialization Training and Bring Up for Die-to-die Interconnect
Intel Corporation
0 cites
US123998322025
Shared Buffered Memory Routing
Intel Corporation
0 cites
US123867682025
Extending Multichip Package Link Off Package
Intel Corporation
0 cites
US123732792025
Selection of Processing Mode for Receiver Circuit
Intel Corporation
0 cites
US123609342025
Parameter Exchange for a Die-to-die Interconnect
Intel Corporation
0 cites
US123623062025
Clock-gating in Die-to-die (D2D) Interconnects
Intel Corporation
0 cites
US123533052025
Compliance and Debug Testing of a Die-to-die Interconnect
Intel Corporation
0 cites
US123533292025
System, Apparatus and Methods for Direct Data Reads from Memory
Intel Corporation
0 cites
US123555652025
Low-latency Forward Error Correction for High-speed Serial Links
Intel Corporation
0 cites
US123327522025
Hardware Logging for Lane Margining and Characterization
Intel Corporation
0 cites
US123328262025
Die-to-die Interconnect
Intel Corporation
0 cites
US123213052025
Sideband Interface for Die-to-die Interconnects
Intel Corporation
0 cites
US123163432025
Phy-based Retry Techniques for Die-to-die Interfaces
Intel Corporation
0 cites
US123164462025
Latency Optimization in Partial Width Link States
Intel Corporation
0 cites
US122598352025
Disaggregation of Computing Devices Using Enhanced Retimers with Circuit Switching
Intel Corporation
0 cites
US122423362025
Multi-protocol Support on Common Physical Layer
Intel Corporation
0 cites
US122443262025
Encoder and Decoder of Forward Error Correction (FEC) Codec
Intel Corporation
0 cites
US122228812025
Logical Physical Layer Interface Specification Support for Pcie 6.0, Cxl 3.0, and UPI 3.0 Protocols
INTEL CORPORATION
0 cites
US122233582025
Connecting Accelerator Resources Using a Switch
Intel Corporation
0 cites
US122166072025
Source Ordering in Device Interconnects
Intel Corporation
0 cites
US122190382025
Alternate Protocol Negotiation in a High Performance Interconnect
Intel Corporation
0 cites
US121973572025
High Performance Interconnect
Intel Corporation
0 cites
US121894702025
Forward Error Correction and Cyclic Redundancy Check Mechanisms for Latency-critical Coherency and Memory Interconnects
Intel Corporation
0 cites
US121895502025
High Performance Interconnect
Intel Corporation
0 cites
US121644572024
Negotiating Asymmetric Link Widths Dynamically in a Multi-lane Link
Intel Corporation
0 cites
US121554742024
Characterizing and Margining Multi-voltage Signal Encoding for Interconnects
Intel Corporation
0 cites
US121355812024
System, Method, and Apparatus for SRIS Mode Selection for PCIE
Intel Corporation
0 cites
US120994582024
Pooled Memory Address Translation
Intel Corporation
0 cites
US120560292024
In-system Validation of Interconnects by Error Injection and Measurement
Intel Corporation
0 cites
US119342612024
Flit-based Parallel-forward Error Correction and Parity
Intel Corporation
0 cites
US118863122024
Characterizing Error Correlation Based on Error Logging for Computer Buses
Intel Corporation
0 cites
US118608122024
Serdes Link Training
0 cites
US118418202023
Precoding Mechanism in Pci-express
Intel Corporation
0 cites
US118361012023
Partial Link Width States for Bidirectional Multilane Links
Intel Corporation
0 cites
US118180582023
Shared Resources for Multiple Communication Traffics
Intel Corporation
0 cites
US117898922023
Recalibration of PHY Circuitry for the PCI Express (PIPE) Interface Based on Using a Message Bus Interface
Intel Corporation
0 cites
US117701382023
Encoder and Decoder of Forward Error Correction (FEC) Codec
Intel Corporation
0 cites
US117628022023
Streaming Fabric Interface
Intel Corporation
0 cites
US117554862023
Shared Buffered Memory Routing
Intel Corporation
0 cites
US117580282023
Alternate Protocol Negotiation in a High Performance Interconnect
Intel Corporation
0 cites
US117409582023
Multi-protocol Support on Common Physical Layer
Intel Corporation
0 cites
US117410302023
High Performance Interconnect
Intel Corporation
0 cites
US117431092023
Link Layer Communication by Multiple Link Layer Encodings for Computer Buses
Intel Corporation
0 cites
US117269392023
Flex Bus Protocol Negotiation and Enabling Sequence
Intel Corporation
0 cites
US117290962023
Techniques to Support Multiple Protocols Between Computer System Interconnects
Intel Corporation
0 cites
US116750032023
Interconnect Retimer Enhancements
Intel Corporation
0 cites
US116694812023
Enabling Sync Header Suppression Latency Optimization in the Presence of Retimers for Serial Interconnect
Intel Corporation
0 cites
US116570152023
Multiple Uplink Port Devices
Intel Corporation
0 cites
US116376572023
Low-latency Forward Error Correction for High-speed Serial Links
Intel Corporation
0 cites
US116304802023
System, Method, and Apparatus for SRIS Mode Selection for Pcie
Intel Corporation
0 cites
US116321302023
PCI Express Enhancements
Intel Corporation
0 cites
US115994972023
High Performance Interconnect
Intel Corporation
0 cites
US115953182023
Ordered Sets for High-speed Interconnects
Intel Corporation
0 cites
US115739202023
SERDES Link Training
Intel Corporation
0 cites
US115619102023
In-band Retimer Register Access
Intel Corporation
0 cites