Patents/Inventors

Dean D. Gans

Nampa, IDUS45 patents

34 Patents

US126023272026
Counter-based Prefetch Management for Memory
0 cites
US125874182026
Multiplexing Distinct Signals on a Single Pin of a Memory Device
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US125734432026
Apparatuses and Methods for a Multi-bit Duty Cycle Monitor
0 cites
US124685892025
Methods for Activity-based Memory Maintenance Operations and Memory Devices and Systems Employing the Same
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US124230102025
Memory Devices with Multiple Sets of Latencies and Methods for Operating the Same
0 cites
US123475212025
Time Delay Indication for Host in Memory System
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US123145752025
Memory System and Operations of the Same
0 cites
US123080902025
Apparatuses and Methods for Storing and Writing Multiple Parameter Codes for Memory Operating Parameters
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US122654892025
Communicating Data with Stacked Memory Dies
0 cites
US122239982025
Apparatuses and Methods for Input Receiver Circuits and Receiver Masks for Same
0 cites
US121823972024
Apparatuses and Methods for Configurable Memory Array Bank Architectures
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US121833832024
Methods for Row Hammer Mitigation and Memory Devices and Systems Employing the Same
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US121596602024
Methods for Row Hammer Mitigation and Memory Devices and Systems Employing the Same
0 cites
US120017152024
Memory with Virtual Page Size
0 cites
US119718202024
Variable Modulation Scheme for Memory Device Access or Operation
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US119551622024
Apparatuses and Methods for Input Receiver Circuits and Receiver Masks for Same
0 cites
US119559772024
Apparatuses and Methods for Duty Cycle Adjustment of a Semiconductor Device
0 cites
US119474122024
Methods for Activity-based Memory Maintenance Operations and Memory Devices and Systems Employing the Same
0 cites
US119148742024
Memory Devices with Multiple Sets of Latencies and Methods for Operating the Same
0 cites
US119157882024
Indication in Memory System or Sub-system of Latency Associated with Performing an Access Command
0 cites
US119075462024
Memory System and Operations of the Same
0 cites
US119010372024
Apparatuses and Methods for Storing and Writing Multiple Parameter Codes for Memory Operating Parameters
0 cites
US118940442024
Apparatuses and Methods for a Multi-bit Duty Cycle Monitor
0 cites
US118372722023
Methods for Row Hammer Mitigation and Memory Devices and Systems Employing the Same
0 cites
US118224772023
Prefetch Management for Memory
0 cites
US118106102023
Methods for Row Hammer Mitigation and Memory Devices and Systems Employing the Same
0 cites
US117754602023
Communicating Data with Stacked Memory Dies
0 cites
US116987262023
Apparatuses and Methods for Configurable Memory Array Bank Architectures
Micron Technology, Inc.
0 cites
US116824472023
Apparatuses and Methods for Input Receiver Circuits and Receiver Masks for Same
Micron Technology, Inc.
0 cites
US116106132023
Multiple Concurrent Modulation Schemes in a Memory System
Micron Technology, Inc.
0 cites
US116046062023
Prefetch Signaling in Memory System or Subsystem
Micron Technology, Inc.
0 cites
US115994742023
Stacked Memory Dice for Combined Access Operations
Micron Technology, Inc.
0 cites
US115689062023
Apparatuses and Methods for Storing and Writing Multiple Parameter Codes for Memory Operating Parameters
Micron Technology, Inc.
0 cites
US115506502023
Methods for Activity-based Memory Maintenance Operations and Memory Devices and Systems Employing the Same
Micron Technology, Inc.
0 cites