Patents/Inventors

David Matthew Thompson

Dallas, TXUS50 patents

44 Patents

US126194572026
Merging Data for Write Allocate
Texas Instruments Incorporated
0 cites
US126137312026
Pipeline Arbitration
Texas Instruments Incorporated
0 cites
US125724162026
Error Correcting Codes for Multi-master Memory Controller
TEXAS INSTRUMENTS INCORPORATED
0 cites
US125612552026
Prefetch Kill and Revival in an Instruction Cache
Texas Instruments Incorporated
0 cites
US125050152025
Pipelined Read-modify-write Operations in Cache Memory
Texas Instruments Incorporated
0 cites
US124935222025
Write Control for Read-modify-write Operations in Cache Memory
Texas Instruments Incorporated
0 cites
US124617752025
Controller with Caching and Non-caching Modes
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123732862025
Handling Non-correctable Errors
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123327902025
Multi-level Cache Security
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123212702025
Hardware Coherence for Memory Controller
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123212772025
Prefetch Management in a Hierarchical Cache System
TEXAS INSTRUMENTS INCORPORATED
0 cites
US122713142025
Cache Size Change
Texas Instruments Incorporated
0 cites
US122171022025
Distributed Mechanism for Fine-grained Test Power Control
TEXAS INSTRUMENTS INCORPORATED
0 cites
US121973312025
Hardware Coherence Signaling Protocol
Texas Instruments Incorporated
0 cites
US121973322025
Memory Pipeline Control in a Hierarchical Memory System
Texas Instruments Incorporated
0 cites
US121473012024
Parallelized Scrubbing Transactions
TEXAS INSTRUMENTS INCORPORATED
0 cites
US121416012024
Global Coherence Operations
Texas Instruments Incorporated
0 cites
US121356462024
Cache Coherence Shared State Suppression
Texas Instruments Incorporated
0 cites
US120860642024
Aliased Mode for Cache Controller
Texas Instruments Incorporated
0 cites
US120560512024
Tag Update Bus for Updated Coherence State
Texas Instruments Incorporated
0 cites
US120456442024
Pseudo-random Way Selection
Texas Instruments Incorporated
0 cites
US120388402024
Multi-level Cache Security
Texas Instruments Incorporated
0 cites
US120195142024
Handling Non-correctable Errors
Texas Instruments Incorporated
0 cites
US120142062024
Pipeline Arbitration
Texas Instruments Incorporated
0 cites
US120012822024
Write Control for Read-modify-write Operations in Cache Memory
Texas Instruments Incorporated
0 cites
US120013512024
Multiple-requestor Memory Access Pipeline and Arbiter
Texas Instruments Incorporated
0 cites
US119774912024
Prefetch Kill and Revival in an Instruction Cache
Texas Instruments Incorporated
0 cites
US119409182024
Memory Pipeline Control in a Hierarchical Memory System
Texas Instruments Incorporated
0 cites
US119216372024
Write Streaming with Cache Write Acknowledgment in a Processor
Texas Instruments Incorporated
0 cites
US119077532024
Controller with Caching and Non-caching Modes
Texas Instruments Incorporated
0 cites
US118160322023
Cache Size Change
Texas Instruments Incorporated
0 cites
US117898682023
Hardware Coherence Signaling Protocol
Texas Instruments Incorporated
0 cites
US117687332023
Error Correcting Codes for Multi-master Memory Controller
Texas Instruments Incorporated
0 cites
US117626832023
Merging Data for Write Allocate
Texas Instruments Incorporated
0 cites
US117409302023
Global Coherence Operations
Texas Instruments Incorporated
0 cites
US117204952023
Multi-level Cache Security
Texas Instmments Incorporated
0 cites
US117147542023
Shadow Caches for Level 2 Cache Controller
Texas Instruments Incorporated
0 cites
US116874572023
Hardware Coherence for Memory Controller
Texas Intruments Incorporated
0 cites
US116757002023
Cache Coherence Shared State Suppression
Texas Instruments Incorporated
0 cites
US116756602023
Parallelized Scrubbing Transactions
Texas Instruments Incorporated
0 cites
US116202362023
Prefetch Kill and Revival in an Instruction Cache
Texas Instruments Incorporated
0 cites
US116098182023
Pipelined Read-modify-write Operations in Cache Memory
Texas Instruments Incorporated
0 cites
US115800242023
Memory Pipeline Control in a Hierarchical Memory System
Texas Instruments Incorporated
0 cites
US115678742023
Prefetch Management in a Hierarchical Cache System
Texas Instruments Incorporated
0 cites