13 Patents
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- US123289272025Low Resistance and Reduced Reactivity Approaches for Fabricating Contacts and the Resulting Structures
Intel Coporation
0 cites - US123226992025Method of Forming High Density, High Shorting Margin, and Low Capacitance Interconnects by Alternating Recessed Trenches
Tahoe Research, Ltd.
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- US120338962024Isolation Wall Stressor Structures to Improve Channel Stress and Their Methods of Fabrication
Intel Corporation
0 cites - US118698942024Metallization Structures for Stacked Device Connectivity and Their Methods of Fabrication
Intel Corporation
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- US118307682023Integrated Circuits with Line Breaks and Line Bridges Within a Single Interconnect Level
Intel Corporation
0 cites - US116520672023Methods of Forming Substrate Interconnect Structures for Enhanced Thin Seed Conduction
Intel Corporation
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- US115575362023Integrated Circuits (ic's) with Electro-migration (em)—resistant Segments in an Interconnect Level
Intel Corporation
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