Chong J. Zhao

5 Patents

• US123408632025

  Stacked Memory Chip Solution with Reduced Package Inputs/outputs (i/os)

  Intel Corporation

  0 cites
• US120873522024

  Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate

  Tahoe Research, Ltd.

  0 cites
• US120739062024

  Package Pin Pattern for Device-to-device Connection

  Intel Corporation

  0 cites
• US117766192023

  Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate

  Tahoe Research, Ltd.

  0 cites
• US115573332023

  Techniques to Couple High Bandwidth Memory Device on Silicon Substrate and Package Substrate

  Tahoe Research, Ltd.

  0 cites