Patents/Inventors

Chieh-jen Ku

Portland, ORUS30 patents

26 Patents

US125990322026
Bilayer Memory Stacking with Lines Shared Between Bottom and Top Memory Layers
Intel Corporation
0 cites
US125139702025
Integrated Circuits with Tungsten Interconnect Liners
Intel Corporation
0 cites
US124713182025
Low Defect, High Mobility Thin Film Transistors with In-situ Doped Metal Oxide Channel Material
Intel Corporation
0 cites
US124462082025
Multilevel Wordline Assembly for Embedded DRAM
Intel Corporation
0 cites
US124262472025
Capacitor Connections in Dielectric Layers
Intel Corporation
0 cites
US123763422025
Passivation Layers for Thin Film Transistors
Intel Corporation
0 cites
US123100012025
Decoupling Capacitors and Methods of Fabrication
Intel Corporation
0 cites
US122389132025
Two Transistor Memory Cell Using Stacked Thin-film Transistors
Intel Corporation
0 cites
US121762842024
Through Plate Interconnect for a Vertical MIM Capacitor
Intel Corporation
0 cites
US121487342024
Transistors, Memory Cells, and Arrangements Thereof
Intel Corporation
0 cites
US121502972024
Thin Film Transistors Having a Backside Channel Contact for High Density Memory
Intel Corporation
0 cites
US120806432024
Integrated Circuit Structures Having Differentiated Interconnect Lines in a Same Dielectric Layer
Intel Corporation
0 cites
US120807812024
Fabrication of Thin Film Fin Transistor Structure
Intel Corporation
0 cites
US119918732024
Capacitor Separations in Dielectric Layers
Intel Corporation
0 cites
US119731052024
Embedded Precision Resistor for Non-planar Semiconductor Device Architectures
Intel Corporation
0 cites
US119555602024
Passivation Layers for Thin Film Transistors and Methods of Fabrication
Intel Corporation
0 cites
US119294152024
Thin Film Transistors with Offset Source and Drain Structures and Process for Forming Such
Intel Corporation
0 cites
US119089112024
Thin Film Transistors with Raised Source and Drain Contacts and Process for Forming Such
Intel Corporation
0 cites
US118324382023
Capacitor Connections in Dielectric Layers
Intel Corporation
0 cites
US118109802023
Channel Formation for Three Dimensional Transistors
Intel Corporation
0 cites
US117840882023
Isolation Gap Filling Process for Embedded Dram Using Spacer Material
Intel Corporation
0 cites
US117587112023
Thin-film Transistor Embedded Dynamic Random-access Memory with Shallow Bitline
Intel Corporation
0 cites
US116839292023
Method for Making Memory Cells Based on Thin-film Transistors
Intel Corporation
0 cites
US116520472023
Intermediate Separation Layers at the Back-end-of-line
Intel Corporation
0 cites
US116108942023
Capacitor Separations in Dielectric Layers
Intel Corporation
0 cites
US115631072023
Method of Contact Patterning of Thin Film Transistors for Embedded DRAM Using a Multi-layer Hardmask
Intel Corporation
0 cites