Charles Jay Alpert

14 Patents

• US125858582026

  Grid Cell Routing Capacity Adjustment Based on Pin Density

  Cadence Design Systems, Inc.

  0 cites
• US125358502026

  Clock Gate Cloning Based on Clocked Circuit Element Switching Activity

  Cadence Design Systems, Inc.

  0 cites
• US125363612026

  Network Assignment Based on Non-default Design Rules

  Cadence Design Systems, Inc.

  0 cites
• US125363622026

  API for Restructuring a Post-cts Clock Tree to Include User-identified Clock Instances

  Cadence Design Systems, Inc.

  0 cites
• US125052742025

  Detecting and Modeling via During Global Routing

  Cadence Design Systems, Inc.

  0 cites
• US125052772025

  Cell-based Pin Access Location Generation

  Cadence Design Systems, Inc.

  0 cites
• US124304892025

  Restructuring Algorithm for Including User-specified Clock Instances in a Post-cts Clock Tree

  Cadence Design Systems, Inc.

  0 cites
• US124234992025

  Resistance and Capacitance Aware Preferred Layer Trimming

  Cadence Design Systems, Inc.

  0 cites
• US124235012025

  Skewing Level Limited Clock Tree

  Cadence Design Systems, Inc.

  0 cites
• US123937602025

  Wire Density-aware Layer Assignment

  Cadence Design Systems, Inc.

  0 cites
• US123937632025

  Timing-based Layer Assignment

  Cadence Design Systems, Inc.

  0 cites
• US123397012025

  Insertion Delay and Area Tradeoff for Buffering Solution Selection in Clock Tree Synthesis

  Cadence Design Systems, Inc.

  0 cites
• US123211932025

  Hierarchically-aware Buffering for Clock Structures

  Cadence Design Systems, Inc.

  0 cites
• US120618572024

  Post-cts Insertion Delay and Skew Target Reformulation of Clock Tree

  Cadence Design Systems, Inc.

  0 cites