Patents/Inventors

Charan V. Surisetty

Clifton Park, NYUS1 patent

3 Patents

US122373282025
Minimizing Shorting Between Finfet Epitaxial Regions
Adeia Semiconductor Solutions LLC
0 cites
US122373682025
Semiconductor Structures Including Middle-of-line (MOL) Capacitance Reduction for Self-aligned Contact in Gate Stack
Adeia Semiconductor Solutions LLC
0 cites
US116643752023
Minimizing Shorting Between Finfet Epitaxial Regions
Tessera LLC
0 cites